ESD标准

METHOD 3015.7

ELECTROSTATIC DISCHARGE SENSITIVITY CLASSIFICATION

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1. PURPOSE. This method establishes the procedure for classifying microcircuits according to their susceptibility to damageor degradation by exposure to electrostatic discharge (ESD). This classification is used to specify appropriate packaging andhandling requirements in accordance with MIL-PRF--38535, and to provide classification data to meet the requirements ofMIL-STD-1686.

1.1 Definition. The following definition shall apply for the purposes of this test method.

1.1.1 Electrostatic discharge (ESD). A transfer of electrostatic charge between two bodies at different electrostatic potentials.2. APPARATUS.2.1 Test apparatus. ESD pulse simulator and device under test (DUT) socket equivalent to the circuit of figure 3015-1, andcapable of supplying pulses with the characteristics required by figure 3015-2.

2.2 Measurement equipment. Equipment including an oscilloscope and current probe to verify conformance of the simulatoroutput pulse to the requirements of figure 3015-2.

2.2.1 Oscilloscope and amplifier. The oscilloscope and amplifier combination shall have a 350 MHz minimum bandwidth and avisual writing speed of 4 cm/ns minimum.

2.2.2 Current probe. The current probe shall have a minimum bandwidth of 350 MHz (e.g., Tektronix CT-1 at 1,000 MHz).2.2.3 Charging voltage probe. The charging voltage probe shall have a minimum input resistance of 1,000 M6and a divisionratio of 4 percent maximum (e.g., HP 34111A).

2.3 Calibration. Periodic calibration shall include but not be limited to the following.2.3.1 Charging voltage. The meter used to display the simulator charging voltage shall be calibrated to indicate the actualvoltage at points C and D of figure 3015-1, over the range specified in table I.

2.3.2 Effective capacitance. Effective capacitance shall be determined by charging C1 to the specified voltage (with table I),with no device in the test socket and the test switch open, and by discharging C1 into an electrometer, coulombmeter, or

calibrated capacitor connected between points A and B of figure 3015-1. The effective capacitance shall be 100 pF ±10 percentover the specified voltage range and shall be periodically verified at 1,000 volts. (Note: A series resistor may be needed to slowthe discharge and obtain a valid measurement.)

2.3.3 Current waveform. The procedure of 3.2 shall be performed for each voltage step of table I. The current waveform ateach step shall meet the requirements of figure 3015-2.

2.4 Qualification. Apparatus acceptance tests shall be performed on new equipment or after major repair. Testing shallinclude but not be limited to the following.

2.4.1 Current waveform verification. Current waveform shall be verified at every pin of each test fixture using the pin nearestterminal B (see figure 3015-1) as the reference point. All waveforms shall meet the requirements of figure 3015-2. The pin pairrepresenting the worst case (closest to the limits) waveform shall be identified and used for the verification required by 3.2.3. PROCEDURE.3.1 General.3.1.1 Test circuit. Classification testing shall be performed using a test circuit equivalent to figure 3015-1 to produce thewaveform shown on figure 3015-2.METHOD 3015.722 March 1989

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3.1.2 Test temperature. Each device shall be stabilized at room temperature prior to and during testing.3.1.3 ESD classification testing. ESD classification testing of devices shall be considered destructive.

3.2 ESD simulator current waveform verification. To ensure proper simulator operation, the current waveform verificationprocedure shall be done, as a minimum, at the beginning of each shift when ESD testing is performed, or prior to testing aftereach change of the socket/board, whichever is sooner. If the simulator does not meet all requirements, all classification testingdone since the last successful verification shall be repeated. At the time of initial facility certification and recertifications,

photographs shall be taken of the waveforms observed as required by 3.2c through 3.2e and be kept on file for purposes of auditand comparison. (Stored digitized representations of the waveforms are acceptable in place of photographs.)

a.b.c.d.e.f.

With the DUT socket installed on the simulator, and with no DUT in the socket, place a short (figure 3015-1) acrosstwo pins of the DUT socket and connect one of the pins to simulator terminal A and the other pin to terminal B.Connect the current probe around the short near terminal B (see figure 3015-1). Set the simulator charging voltagesource VS to 4,000 volts corresponding to step 4 of table I.

Initiate a simulator pulse and observe the leading edge of the current waveform. The current waveform shall meet therise time, peak current, and ringing requirements of figure 3015-2.

Initiate a simulator pulse again and observe the complete current waveform. The pulse shall meet the decay time andringing requirement of figure 3015-2.

Repeat the above verification procedure using the opposite polarity(VS = -4,000 volts).

It is recommended that the simulator output be checked to verify that there is only one pulse per initiation, and thatthere is no pulse while capacitor C1 is being charged. To observe the recharge transient, set the trigger to theopposite polarity, increase the vertical sensitivity by approximately a factor of 10, and initiate a pulse.

TABLE I. Simulator charging voltage (VS) steps versus peak current (IP). 1/

Step 1 2 3 4 VS (volts) 500 1,000 2,000 4,000IP (amperes) 0.33 0.67 1.33 2.671/IP is the current flowing through R2 during

the current waveform verification procedureand which is approximately VS/1,500 ohms.

3.3 Classification testing.a.

A sample of devices (see 4.c) shall be characterized for the device ESD failure threshold using the voltage steps shown intable I, as a minimum. Finer voltage steps may optionally be used to obtain a more accurate measure of the failure voltage.Testing may begin at any voltage step, except for devices which have demonstrated healing effects, including those with sparkgap protection, which shall be started at the lowest step. Examination of known technology family input or output V/I damagecharacteristics (i.e., curve tracer), or other simplified test verification techniques may be used to validate the failure threshold(e.g., cumulative damage effects may be eliminated by retesting at the failure voltage step using a new sample of devices andpossibly passing the step).

METHOD 3015.122 March 1989

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MIL-STD-883E

b.

A new sample of devices shall be selected and subjected to the next lower voltage step used. Each device shall be testedusing three positive and three negative pulses using each of the pin combinations shown in table II. A minimum of 1 seconddelay shall separate the pulses.

The sample devices shall be electrically tested to subgroups 1 and 7 as applicable (room temperature dc parameters andfunctional tests).

If one or more of the devices fail, the testing of 3.3b and 3.3c shall be repeated at the next lower voltage step used.

If none of the devices fail, record the failure threshold determined in 3.3a. Note the highest step passed, and use it to classifythe device according to table III.

TABLE II. Pin combinations to be tested. 1/ 2/ Terminal A (Each pin individually connected to terminal A with the other floating) 1. 2. All pins except Vps1 3/ All input and output pins Terminal B (The common combination of all like-named pins connected to terminal B) All Vps1 pins All other input-output pinsc.d.e.

1/ Table II is restated in narrative form in 3.4 below.2/ No connects are not to be tested.3/ Repeat pin combination 1 for each named power supply and for ground (e.g., where Vps1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc.)

3.4 Pin combination to be tested.a.Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except

the one being tested and the ground pin(s) shall be open.b.

Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins(e.g., VSS1 or VSS2 or VSS3 or VCC1 or VCC2) connected to terminal B. All pins except the one being tested and the power supplypin or set of pins shall be open.

Each input and each output individually connected to terminal A with respect to a combination of all the other input and outputpins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input andoutput pins shall be open.

TABLE III. Device ESD failure threshold classification. Class 1 Class 2 Class 3 0 volt to 1,999 volts 2,000 volts to 3,999 volts 4,000 volts and abovec.

METHOD 3015.722 March 1989

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MIL-STD-883E

4. SUMMARY. The following details shall be specified in the applicable purchase order or contract, if other than specifiedherein.

a.b.Post test electricals.

Special additional or substitute pin combinations, if applicable.c.

Sample size, if other than three devices.

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MIL-STD-883E

R1 = 106 ohms to 107 ohms

C1 = 100 picofarads ±10 percentR2 = 1,500 ohms ±1 percentS1 = High voltage relay

S2 = Normally closed switch

(Insulation resistance 1012 ohms minimum)

(Bounceless, mercury wetted, or equivalent)

(Open during discharge pulse and capacitance measurement)

NOTES:

1.The performance of this simulator circuit is strongly influenced by parasitics. Capacitances across relays and

resistor terminals, and series inductance in wiring and in all components shall be minimized.

2.As a precaution against transients upon recharge of C1, the supply voltage VS may be reduced before switch S1 is

returned to the charging position.

3.Piggybacking DUT sockets is not permitted during verification or classification testing.

4.Switching terminals A and B internal to the simulator to obtain opposite polarity is not recommended.5.C1 represents the effective capacitance (see 2.3.2).

6.The current probe connection shall be made with double shielded cable into a 50-ohm termination at the

oscilloscope. The cable length shall not exceed 3 feet.

FIGURE 3015-1. EDS classification test circuit (human body model).

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MIL-STD-883E

NOTES:

1.The current waveforms shown shall be measured as described in the waveform verification procedure of 3.2,

using equipment meeting the requirements of 2.

2.The current pulse shall have the following characteristics:

Tri (rise time)---------------Less than 10 nanoseconds.Tdi (delay time)-------------150 ±20 nanoseconds.

Ip (peak current)------------Within ±10 percent of the Ip value shown in table II for the voltage step selected.Ir (ringing)--------------------The decay shall be smooth, with ringing, break points, double time constants or

discontinuities less than 15 percent Ip maximum, but not observable 100nanoseconds after start of the pulse.

FIGURE 3015-2. EDS classification test circuit waveforms (human body model).METHOD 3015.122 March 1989

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