EN29LV400A

2021-09-18 来源：榕意旅游网

EN29LV400A

EN29LV400A 4 Megabit (512K x 8-bit / 256K x 16-bit) Flash Memory

Boot Sector Flash Memory, CMOS 3.0 Volt-only FEATURES

• 3V, single power supply operation

- Full voltage range: 2.7-3.6 volt read and write operations for battery-powered applications. - Regulated voltage range: 3.0-3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors.

• High performance

- Access times as fast as 45 ns

• Low power consumption (typical values at 5 MHz)

- 7 mA typical active read current

- 15 mA typical program/erase current

- 1 µA typical standby current (standard access time to active mode)

• Flexible Sector Architecture:

- One 16 K-byte, two 8 K-byte, one 32 K-byte, and seven 64 K-byte sectors (byte mode) - One 8 K-word, two 4 K-word, one 16 K-word and seven 32 K-word sectors (word mode)

• Sector protection:

- Hardware locking of sectors to prevent

program or erase operations within individual sectors

- Additionally, temporary Sector Unprotect allows code changes in previously locked sectors.

• High performance program/erase speed - Byte/Word program time: 8µs typical - Sector erase time: 500ms typical

• JEDEC Standard Embedded Erase and Program Algorithms

• JEDEC standard DATA# polling and toggle bits feature

• Single Sector and Chip Erase • Sector Unprotect Mode

• Erase Suspend / Resume modes:

Read or program another Sector during Erase Suspend Mode

• triple-metal double-poly triple-well CMOS Flash Technology • Low Vcc write inhibit < 2.5V • minimum 1,000K program/erase endurance cycle

• Package Options - 48-pin TSOP (Type 1) - 48-ball 6mm x 8mm FBGA

• Commercial and Industrial Temperature Range

GENERAL DESCRIPTION

The EN29LV400A is a 4-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 524,288 bytes or 256,144 words. Any byte can be programmed typically in 8µs. The EN29LV400A features 3.0V voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems.

The EN29LV400A has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#) controls, which eliminate bus contention issues. This device is designed to allow either single Sector or full chip erase operation, where each Sector can be individually protected against

program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.

Rev. A, Issue Date: 2005/01/07

EN29LV400ACONNECTION DIAGRAMS

A15 1 A14 2 A13 3 4 A12 A11 5 A10 6 A9 7 A8 8 NC 9 NC 10 11 WE# RESET# 12 NC 13 14 NC RY/BY# 15 16 NC A17 17 18 A7 19 A6 A5 20 21 A4 22 A3 23 A2 24 A1

StandardTSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# Vss

DQ15/A-1DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0

FBGA Top View, Balls Facing Down A6 A13 B6 A12 C6 A14 D6A15 E6 A16 F6 G6H6Vss BYTE#DQ15/A-1A5 B5 C5 D5E5 F5 G5H5A9 A4A8 B4A10 C4A11 D4NC DQ7E4DQ14F4DQ13G4DQ6 H4 WE# RESET# NC DQ5DQ12VccDQ4A3 B3 C3 D3E3 F3 G3H3DQ3H2DQ1 H1Vss RY/BY#A2 A7 A1 NCB2 A17 B1 NC NCD2A5 D1DQ2E2 DQ10F2 DQ11G2C2 A6 C1 DQ0E1DQ8F1DQ9G1 A3 A4 A2 A1A0CE#OE#

Rev. A, Issue Date: 2005/01/07

EN29LV400A

TABLE 1. PIN DESCRIPTION

Pin Name

Function

FIGURE 1. LOGIC DIAGRAM

EN29LV400A

DQ0 – DQ15A0-A17 Addresses DQ0-DQ14 15 Data Inputs/Outputs

A0 - A17 (A-1)DQ15 / A-1

DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)

CE# Chip Enable Reset#CE#OE# Output Enable OE#RESET#

Hardware Reset Pin

WE#RY/BY# Byte# RY/BY# Ready/Busy Output WE# Write Enable Vcc Supply Voltage Vss Ground NC

Not Connected to anything

BYTE# Byte/Word Mode

3Rev. A, Issue Date: 2005/01/07

EN29LV400A

TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE

Sector

SECTOR SIZE (Kbytes /

(X16) (X8) Kwords)

ADDRESS RANGE

A17A16A15A14 A13 A1210 3E000h-3FFFFh 7C000h-7FFFFh 16/8 1 1 1 1 1 X 9 3D000h-3DFFFh 7A000h-7BFFFh 8/4 1 1 1 1 0 1 8 3C000h-3CFFFh 78000h-79FFFh 8/4 1 1 1 1 0 0 7 6 5 4 3 2 1 0

38000h-3BFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 00000h-07FFFh

70000h – 77FFFh60000h - 6FFFFh50000h – 5FFFFh40000h – 4FFFFh30000h – 3FFFFh20000h - 2FFFFh10000h - 1FFFFh00000h - 0FFFFh

32/16 64/32 64/32

1 1 1

1 1 0

1 0 1

0 X X

X X X

64/32 1 0 0 X X X 64/32 64/32 64/32 64/32

0 0 0 0

1 1 0 0

1 0 1 0

X X X X

Rev. A, Issue Date: 2005/01/07

EN29LV400A

TABLE 2B. BOTTOM BOOT BLOCK SECTOR ARCHITECTURE

Sector

SECTOR SIZE (Kbytes/

(X16) (X8) Kwords)

ADDRESS RANGE

A17A16A15A14 A13 A1210 38000h-3FFFFh 70000h –7FFFFh 64/32 1 1 1 X X X 9 8 7 6 5 4 3

30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 04000h-07FFFh

60000h – 6FFFFh50000h – 5FFFFh40000h – 4FFFFh30000h – 3FFFFh20000h – 2FFFFh10000h – 1FFFFh08000h – 0FFFFh

64/32 1 1 0 X X X 64/32

64/32 1 0 0 X X X 64/32

64/32 0 1 0 X X X 64/32

32/16 0 0 0 1 X X 8/4 0 0 0 0 1 1 8/4 0 0 0 0 1 0 16/8 0 0 0 0 0 X 2 03000h-03FFFh 06000h – 07FFFh1 02000h-02FFFh 04000h – 05FFFh0 00000h-01FFFh 00000h – 03FFFh

or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400APRODUCT SELECTOR GUIDE

Product Number Speed Option

Regulated Voltage Range: Vcc=3.0-3.6 VFull Voltage Range: Vcc=2.7 – 3.6 V

EN29LV400A

-45R -55R

-70 -90 45 55 70 90 45 55 70 90 25 30 30 35 Max Access Time, ns (tacc) Max CE# Access, ns (tce) Max OE# Access, ns (toe)

BLOCK DIAGRAM

Vcc Vss RY/BY# Block Protect SwitchesDQ0-DQ15 (A-1)Erase Voltage GeneratorState Control Program Voltage GeneratorChip EnableOutput EnableLogicInput/Output BuffersWE# Command Register CE# OE# STB Data LatchY-DecoderAddress LatchSTBY-GatingVcc Detector TimerX-DecoderCell MatrixA0-A17

Rev. A, Issue Date: 2005/01/07

EN29LV400A

TABLE 3. OPERATING MODES

4M FLASH USER MODE TABLE

Operation CE# OE# WE#Reset# A0-A17Read L L H H AINWrite L H L H AINCMOS Standby Vcc ± 0.3V X X Vcc ± 0.3VX TTL Standby H X X H X Output Disable L H H H X Hardware Reset X X X L X Temporary Sector

AINUnprotect X X X VID

DQ8-DQ15 Byte# Byte#

DQ0-DQ7 = VIH= VILDOUTDOUTHigh-ZDINDINHigh-ZHigh-Z High-Z High-ZHigh-Z High-Z High-ZHigh-Z High-Z High-ZHigh-Z High-Z High-ZDIN

DIN

Notes:

L=logic low= VIL, H=Logic High= VIH, VID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), DIN=Data In, DOUT=Data Out, AIN=Address In

TABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)

4M FLASH MANUFACTURER/DEVICE ID TABLE

A11 A92Description Mode A17 OE WE to CEto A12A10Manufacturer ID: L L H X X VIDEon Device ID Word L L H X X VID(top boot Byte L L H block) Device ID (bottom boot block) A8A7A6A5 to A2XXXA1 A0 DQ8 to DQ15L L X L L H H 22h 22h DQ7 to DQ0 1Ch B9h BAh 01h (Protected) H1XXXXXLLLX B9h X BAh X Word L L H X X VIDByte L L H L L H SA X VIDSector Protection Verification

XXLXH L X 00h (Unprotected)Note:

1. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. A further Manufacturing ID must be read with A8=H.

2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.

Rev. A, Issue Date: 2005/01/07

EN29LV400AUSER MODE DEFINITIONS

Word / Byte Configuration

The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.

On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Standby Mode

The EN29LV400A has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical). It is placed in CMOS-compatible standby when the CE# pin is at VCC ± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at VIH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input.

Read Mode

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more additional information.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” additional details.

Output Disable Mode

When the OE# pin is at a logic high level (VIH), the output from the EN29LV400A is disabled. The output pins are placed in a high impedance state.

Auto Select Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID (10.5V to 11.5 V) on address pin A9. Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.

Rev. A, Issue Date: 2005/01/07

EN29LV400ATo access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.

Write Mode

Write operations, including programming data and erasing sectors of memory, require the host system to write a command or command sequence to the device. Write cycles are initiated by placing the byte or word address on the device’s address inputs while the data to be written is input on DQ[7:0] in Byte Mode (BYTE# = L) or on DQ[15:0] in Word Mode (BYTE# = H). The host system must drive the CE# and WE# pins Low and the OE# pin high for a valid write operation to take place. All addresses are latched on the falling edge of WE# and CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. The system is not required to provide further controls or timings. The device automatically provides internally generated program / erase pulses and verifies the programmed /erased cells’ margin. The host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits.

The ‘Command Definitions’ section of this document provides details on the specific device commands implemented in the EN29LV400A.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.

There are two methods to enabling this hardware protection circuitry. The first one requires only that the RESET# pin be at VID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings. When doing Sector Unprotect, all the other sectors should be protected first.

The second method is meant for programming equipment. This method requires VID be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This method is described in a separate document called EN29LV400A Supplement, which can be obtained by contacting a representative of Eon Silicon Devices, Inc.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by simply selecting the sector addresses. Once is removed from the RESET# pin, all the previously protected sectors are protected again. See accompanying figure and timing diagrams for more details.

Notes:

1. All protected sectors unprotected.

2. Previously protected sectors protected again.

Start Reset#=VID (note 1) Perform Erase or Program Operations Reset#=VIHTemporary Sector Unprotect Completed (note 2)This Data Sheet may be revised by subsequent versions ©2005 Eon Silicon Solution, Inc., www.essi.com.tw 9or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400AAutomatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tacc + 30ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep more current specification.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.

Low VCC Write Inhibit

When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than VLKO.

Write Pulse “Glitch” protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = VIL, WE# = VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#.

Rev. A, Issue Date: 2005/01/07

EN29LV400ACOMMAND DEFINITIONS

The operations of the EN29LV400A are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.

Table 5. EN29LV400A Command Definitions

Command Sequence

Cycles Bus Cycles

1st

Cycle Addr Data

Cycle AddrData Cycle AddrData Cycle

AddrData Cycle Addr Data Cycle AddrData

Read 1 RA RD Reset 1 xxx F0

Manufacturer

ID Autoselect Device ID Top Boot Device ID Bottom Boot Sector Protect Verify Program

Word 555 2AA

4 AA

Byte AAA 555Word 555 4 AA

Byte AAA

Word 555 4 AA

Byte AAA 2AA

5552AA5552AA

Word 555

4 AA

Byte AAA 555

2AA

5552AA555PA XXX2AA5552AA555

55 55 55

555 90

AAA555 90

AAA

555 90

AAA555

AAA

55 55 PD 00 55 55

100200X01X02X01X02(SA)X02(SA)X04

22B9 B9

22BA

XX00

XX01 00

Word 555 4 AA

Byte AAA

Word 555 Unlock Bypass 3 AA

Byte AAA

Unlock Bypass Program 2 XXX A0 Unlock Bypass Reset 2 XXX 90

Word 555 Chip Erase 6 AA

Byte AAA

Word 555 Sector Erase 6 AA

Byte AAA

Erase Suspend 1 xxx B0 Erase Resume 1 xxx 30 555 A0 PA PD

AAA

555 20

AAA 555 5552AA 555

80 AA 55 10

AAAAAA555 AAA555 5552AA 80 AA 55 SA 30 AAAAAA555

Address and Data values indicated in hex

RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PA

SA = Sector Address: address of the Sector to be erased or verified. Address bits A17-A12 uniquely select any Sector.

Reading Array Data

The device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outputs status data. After completing a programming

Rev. A, Issue Date: 2005/01/07

EN29LV400Aoperation in the Erase Suspend mode, the system may once again read array data with the same exception.

The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See next section for details on Reset.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t-care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires VID on address bit A9 and is intended for PROM programmers.

Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of times, without needing another command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Word / Byte Programming Command

The device may be programmed by byte or by word, depending on the state of the Byte# Pin. Programming the EN29LV400A is performed by using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.

Programming status may be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). ). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.

Rev. A, Issue Date: 2005/01/07

EN29LV400AUnlock Bypass

To speed up programming operation, the Unlock Bypass Command may be used. Once this feature is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the normal four cycle Program Command to program the device. This mode is exited after issuing the Unlock Bypass Reset Command. The device powers up with this feature disabled.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.

Erase Suspend / Resume Command

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase Suspend command.

Rev. A, Issue Date: 2005/01/07

EN29LV400AWhen the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The Autoselect command is not supported during Erase Suspend Mode.

The system must write the Erase Resume command (address bits are don’t-care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

WRITE OPERATION STATUS

DQ7: DATA# Polling

The EN29LV400A provides DATA# polling on DQ7 to indicate the status of the embedded operations. The DATA# polling feature is active during the embedded Programming, Sector Erase, Chip Erase, and Erase Suspend. (See Table 6)

When the embedded Programming is in progress, an attempt to read the device will produce the complement of the data written to DQ7. Upon the completion of the embedded Programming, an attempt to read the device will produce the true data written to DQ7. For the embedded Programming, DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence.

When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the sixth WE# or CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of WE# or CE# pulse for chip erase or sector erase.

DATA# Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (OE#) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts.

The flowchart for DATA# polling (DQ7) is shown on Flowchart 5. The DATA# polling (DQ7) timing diagram is shown in Figure 8.

Rev. A, Issue Date: 2005/01/07

EN29LV400ARY/BY#: Ready/Busy Status output

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to Vcc.

In the output-low period, signifying Busy, the device is actively erasing or programming. This includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

DQ6: Toggle Bit I

The EN29LV400A provides a “Toggle Bit” on DQ6 to indicate the status of the embedded programming and erase operations. (See Table 6)

During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by active OE# and CE#) will result in DQ6 toggling between “zero” and “one”. Once the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During embedded Programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after the rising edge of the sixth WE# pulse for sector erase or chip erase.

In embedded Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read mode without changing data in all protected sectors.

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the DQ6 is toggling after detecting a “1” on DQ5.

The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the output on DQ3 can be used to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) When sector erase starts, DQ3 switches from “0” to “1.” This device does not support multiple sector erase command sequences so it is not very meaningful since it immediately shows as a “1” after the first 30h command. Future devices may support this feature.

DQ2: Erase Toggle Bit II

Rev. A, Issue Date: 2005/01/07

EN29LV400AThe “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to the following table to compare outputs for DQ2 and DQ6.

Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Flowchart 6).

Write Operation Status

Operation

Standard Mode

Embedded Program

Algorithm Embedded Erase AlgorithmReading within Erase Suspended Sector Reading within Non-Erase

Suspended Sector Erase-Suspend Program

DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY#DQ7# Toggle0 1

ToggleNo

Toggle

0 0

N/A 1

No toggle Toggle

0 0

Erase Suspend Mode

0 N/A Toggle 1 Data Data Data Data Data 1 DQ7#

Toggle

N/A

or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400A

Table 6. Status Register Bits

DQ Name Logic Level Definition Erase Complete or

‘1’

erase Sector in Erase suspend

‘0’ Erase On-Going

DATA# Program Complete or 7 POLLING data of non-erase Sector DQ7

during Erase Suspend

DQ7# Program On-Going ‘-1-0-1-0-1-0-1-’Erase or Program On-going

DQ6 Read during Erase Suspend TOGGLE 6 BIT Erase Complete

‘-1-1-1-1-1-1-1-‘

‘1’ Program or Erase Error

5 ERROR BIT ‘0’ Program or Erase On-going

ERASE ‘1’ Erase operation start 3 TIME BIT ‘0’ Erase timeout period on-going

Chip Erase, Erase or Erase suspend on currently

addressed

Sector. (When DQ5=1, Erase

Error due to currently

TOGGLE

2 addressed Sector. Program ‘-1-0-1-0-1-0-1-’

BIT

during Erase Suspend on-going at current address

DQ2

Erase Suspend read on non Erase Suspend Sector

Notes:

DQ7 DATA# Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success.

DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5 Error Bit: set to “1” if failure in programming or erase

DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).

DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.

Rev. A, Issue Date: 2005/01/07

EN29LV400AEMBEDDED ALGORITHMS

Flowchart 1. Embedded Program

STARTWrite Program Command Sequence(shown below) Data# Poll DeviceVerify Data? Increment Address No LastAddress?YesProgramming Done

Flowchart 2. Embedded Program Command Sequence

See the Command Definitions section for more information on WORD mode.

555H / AAH2AAH / 55H 555H / A0H PROGRAM ADDRESS / PROGRAM DATA

Rev. A, Issue Date: 2005/01/07

EN29LV400AFlowchart 3. Embedded Erase

START

Write Erase Command Sequence Data Poll from System or Toggle Bit successfully

completed Data =FFh? No

Yes Erase Done

Flowchart 4. Embedded Erase Command Sequence

See the Command Definitions section for more information on WORD mode.

Chip Erase 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H

Sector Erase

555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H Sector Address/30H

Rev. A, Issue Date: 2005/01/07

EN29LV400A

Start Flowchart 5. DATA# Polling Algorithm

Notes:

(1) This second read is necessary in case the first read was done at the exact instant when the status data was in transition.

Read Data DQ7 = Data? No No DQ5 = 1? Yes Read Data (1) Yes DQ7 = Data? No Fail Yes

Flowchart 6. Toggle Bit Algorithm Notes: (2) This second set of reads is necessary in case the first set of reads was done at the exact instant when the status data was in transition. Pass

Start Read Data twice No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Data twice (2) DQ6 = Toggle? Yes No Fail Pass This Data Sheet may be revised by subsequent versions ©2005 Eon Silicon Solution, Inc., www.essi.com.tw 20or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07 EN29LV400AFlowchart 7a. In-System Sector Protect Flowchart

START PLSCNT = 1RESET# = VIDWait 1 µs NoTemporary Sector Unprotect Mode First WriteCycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector addr with A6 = 0, A1 = 1, A0 = 0 Wait 150 µs Increment PLSCNT Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Reset PLSCNT = 1 Wait 0.4 µs No NoRead from sector address with A6 = 0, A1 = 1, A0 PLSCNT = 25? Data = 01h? Yes Yes Device failed Protect another sector? NoRemove VID from RESET#Write reset command YesSector Protect Algorithm Sector Protect complete This Data Sheet may be revised by subsequent versions ©2005 Eon Silicon Solution, Inc., www.essi.com.tw 21or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400AFlowchart 7b. In-System Sector Unprotect Flowchart

START PLSCNT = 1 Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see Diagram 7a.) RESET# = VIDWait 1 µS First Write Cycle = 60h?YesNo All sectors protected?YesSet up first sector addressNoTemporary Sector Unprotect Mode Sector Unprotect: Write 60H to sector address with A6 = 1, A1 = 1, A0 = 0 Wait 15 ms Increment PLSCNT Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 =0Wait 0.4 µS No PLSCCNT = 1000? Read from sector address with A6 = 1, A1 = 1, A0 = 0 No Data = 00h?Yes Last sector verified? YesRemove VID from RESET#Set up next sector address Sector Unprotect Algorithm

YesDevice failed No Write reset commandSector Unprotect complete This Data Sheet may be revised by subsequent versions ©2005 Eon Silicon Solution, Inc., www.essi.com.tw 22or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400ATable 7. DC Characteristics

(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)

Symbol Parameter Test Conditions Min Max Unit Typ

ILIILOICC1

Input Leakage Current Output Leakage Current Supply Current (read) TTL

(read) CMOS Byte(read) CMOS Word

Supply Current (Standby - TTL)

0V≤ VIN ≤ Vcc 0V≤ VOUT ≤ Vcc CE# = VIL; OE# = VIH;

f = 5MHz CE# = VIH, BYTE# = RESET# =

Vcc ± 0.3V (Note 1) CE# = BYTE# = RESET# = Vcc ± 0.3V

(Note 1)

Byte program, Sector or Chip Erase in progressVIH = Vcc ± 0.3 V VIL = Vss ± 0.3 V

IOL = 4.0 mA IOH = -2.0 mA IOH = -100 µA,

A9 = VID

±1 µA ±1 µA 8

14 12

mA mA

7 12 mA 0.4 1.0 mA ICC2

Supply Current (Standby - CMOS)

ICC3ICC4VILVIHVOLVOHVIDIIDVLKO

Supply Current (Program or Erase)

Automatic Sleep Mode Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS A9 Voltage (Electronic Signature) A9 Current (Electronic Signature)

Supply voltage (Erase and

Program lock-out)

1 5.0 µA 15 30 mA 1 5.0 µA -0.5 0.8 V 0.7 x Vcc ±

Vcc 0.3 0.45 V 0.85 x

V Vcc Vcc -

V 0.4V 10.5 11.5 V 100 µA 2.3 2.5 V

Notes

1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that

they draw power if not at full CMOS supply voltages.

Rev. A, Issue Date: 2005/01/07

EN29LV400ATest Conditions

3.3 V

Device Under Test 2.7 kΩ

CL6.2 kΩ Note: Diodes are IN3064 or equivalent

Test Specifications

Test Conditions Output Load

Output Load Capacitance, CL

Input Rise and Fall times Input Pulse Levels Input timing measurement

reference levels

Output timing measurement

reference levels

5 0.0-3.0 -45R

-55R

-70

-90

Unit

ns V 1 TTL Gate 5

30 30 30 100 pF 0.0-3.0 0.0-3.0 0.0-3.0 1.5 1.5 1.5 1.5 V 1.5 1.5 1.5 1.5 V

or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400A

AC CHARACTERISTICS Hardware Reset (Reset#)

Parameter

Std tREADYtREADYtRPtRH

Description

Reset# Pin Low to Read or Write

Embedded Algorithms

Reset# Pin Low to Read or Write Non Embedded Algorithms

Reset# Pulse Width Reset# High Time Before Read

Test Setup

Speed options Unit-45R-55R-70 -90 Max 20 µsMax 500 nSMin Min

500 50

nSnS

Reset# Timings

RY/BY#

0 V

CE# OE#

RESET#

RY/BY# CE# OE#

RESET#

tRHtRPtREADYReset Timings NOT During Automatic Algorithms

tREADYtRPtRHReset Timings During Automatic Algorithms

Rev. A, Issue Date: 2005/01/07

EN29LV400AAC CHARACTERISTICS

Word / Byte Configuration (Byte#)

Speed UnitStd

Parameter Description -45R-55R-70 -90 tBCSByte# to CE# switching setup time Min 0 0 0 0 ns tCBHCE# to Byte# switching hold time Min 0 0 0 0 ns tRBHRY/BY# to Byte# switching hold time Min 0 0 0 0 ns

CE# OE# Byte# tBCStCBHByte# timings for Read Operations CE# WE# Byte# tRBHtBCSRY/BY# Byte# timings for Write Operations

Note: Switching BYTE# pin not allowed during embedded operations

Rev. A, Issue Date: 2005/01/07

EN29LV400A

Table 8. AC CHARACTERISTICS

Read-only Operations Characteristics

Parameter

Symbols

Description JEDEC Standard

Test

Setup

Speed Options

tAVAVtAVQVtELQVtGLQVtEHQZtGHQZtAXQX

tRCtACCtCEtOEtDFtDFtOH

Read Cycle Time Address to Output Delay Chip Enable To Output Delay Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High ZOutput Hold Time from Addresses, CE# or OE#, whichever occurs first

MinMaxMaxMaxMaxMaxMin

-45R-55R -70 -90 Unit45 55 70 90 ns

CE# = VIL OE#= VILOE#= VIL

45 55 70 90 ns45 55 70 90 ns25 30 30 35 ns10 15 20 20 ns10 15 20 20 ns0 0 0 0 ns

Notes:

For -45R,-55R,70 Vcc = 3.0V ± 5% Output Load : 1 TTL gate and 30pF Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to Vcc Timing Measurement Reference Level, Input and Output: 1.5 V

For all others: Vcc = 3.0V ± 5%

Output Load: 1 TTL gate and 100 pF

Input Rise and Fall Times: 5 ns Input Pulse Levels: 0.0 V to Vcc Timing Measurement Reference Level, Input and Output: 1.5 V

tRCAddresses CE# OE# WE# Outputs Reset# RY/BY# Addresses Stable tACCtDFtOEtOEHtCEOutput Valid tOHHIGH Z 0V

Figure 5. AC Waveforms for READ Operations

Rev. A, Issue Date: 2005/01/07

EN29LV400ATable 9. AC CHARACTERISTICS

Write (Erase/Program) Operations

Parameter Symbols

JEDEC Standard Description

Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable

Hold Time

Read Toggle and Data# Polling

Read Recovery Time before Write (OE# High to WE# Low)

CE# SetupTime CE# Hold Time Write Pulse Width Write Pulse Width High Programming Operation (Word AND Byte Mode)

Speed Options

-45R -55R

-70 -90 Unit tAVAVtAVWLtWLAXtDVWHtWHDX

tWCtAStAHtDStDHtOEStOEHtGHWLtCStCHtWPtWPHtWHWH1tWHWH2tVCStVIDR

Min 45 55 70 90 ns Min 0 0 0 0 ns Min 35 45 45 45 ns Min 20 25 30 45 ns Min 0 0 0 0 ns Min 0 0 0 0 ns MIn 0 0 0 0 ns Min 10 10 10 10 ns Min 0 0 0 0 ns Min 0 0 0 0 ns Min

tGHWLtELWLtWHEHtWLWHtWHDLtWHWH1tWHWH2

Min 25 30 35 45 ns Min 20 20 20 20 ns Typ 8 8 8 8 µs Max 300 300 300 300 µs Sector Erase Operation

Vcc Setup Time Rise Time to VID

Typ 0.5 0.5 0.5 0.5 s Min 50 50 50 50 µs Min

500 500 500 500 ns

or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400A

Table 10. AC CHARACTERISTICS Write (Erase/Program) Operations Alternate CE# Controlled Writes Parameter Symbols Description JEDEC Standard Speed Options tAVAVtAVELtELAXtDVEHtEHDX tWCtAStAHtDStDHtOEStOEHtGHELtWStWHtCPtCPHWrite Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Read Hold Time Toggle and Data# Polling Read Recovery Time before Write (OE High to CE Low) WE# SetupTime WE# Hold Time Write Pulse Width Write Pulse Width High Programming Operation (byte AND word mode) Sector Erase Operation Vcc Setup Time Rise Time to VID-45R -55R-70 -90 Unit Min 45 55 70 90 ns Min 0 0 0 0 ns Min 35 45 45 45 ns Min 20 25 30 45 ns Min 0 0 0 0 ns Min 0 0 0 0 ns Min 0 0 0 0 ns Min 10 10 10 10 ns Min Min Min Min Min Typ Max Typ Min Min 0 0 0 0 ns 0 0 0 0 ns 0 0 0 0 ns 25 30 35 45 ns 20 20 20 20 ns 8 8 8 8 µs 300 300 300 300 µs 0.5 0.5 0.5 0.5 s 50 50 50 50 µs 500 500 500 500 ns tGHELtWLELtEHWHtELEHtEHELtWHWH1tWHWH1tWHWH2tWHWH2 tVCStVIDR

Rev. A, Issue Date: 2005/01/07

EN29LV400A

Table 11. ERASE AND PROGRAMMING PERFORMANCE

Parameter

Limits

Typ Max Unit Comments

Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming

Time

0.5 5 8 8

10 100 300 300 12.6 6.3

sec sec µs µs sec cycles

Excludes 00H programming prior

to erasure

Excludes system level overhead

Byte 4.2 Word 2.1 100K

Erase/Program Endurance

Minimum 100K cycles

Table 12. LATCH UP CHARACTERISTICS

Parameter Description

Min

Max

Input voltage with respect to Vss on all pins except I/O pins

(including A9, Reset and OE#)

Input voltage with respect to Vss on all I/O Pins

Vcc Current

-1.0 V -1.0 V -100 mA

12.0 V Vcc + 1.0 V 100 mA

Note : These are latch up characteristics and the device should never be put under these conditions. Refer to Absolute Maximum ratings for the actual operating limits.

Table 13. TSOP PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

CINCOUTCIN2

Input Capacitance Output Capacitance Control Pin Capacitance

VIN = 0 VOUT = 0 VIN = 0

7.5 9 pF 8 10 pF 9.5 12.5 pF

Table 14. DATA RETENTION

Parameter Description

Test Conditions

Min

Unit

150°C 10 Years Minimum Pattern Data Retention Time

125°C 20 Years

Rev. A, Issue Date: 2005/01/07

EN29LV400AAC CHARACTERISTICS

Figure 6. AC Waveforms for Chip/Sector Erase Operations Timings

Addresses

CE#

Erase Command Sequence (last 2 cycles) tWCtAStAHRead Status Data (last two cycles) 0x2AA SA 0x555 for chip erase tGHWLtCHVA VA

OE#

tWP WE#

tCStWPH

tWHWH2 or tWHWH3

0x55 0x30 Status DOUT Data

tDStDHtBUSYtRB

RY/BY#

VCC

tVCS

Notes:

1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence.

Rev. A, Issue Date: 2005/01/07

EN29LV400A

Figure 7. Program Operation Timings

Program Command Sequence (last 2 cycles) Program Command Sequence (last 2 cycles)

tWCtAStAH

0x555 PA PA PA Addresses CE# tGHWL

tWPOE# tCH WE# tWPH

tCStWHWH1

Data OxA0 PD StatusDOUT tDStRB tBUSYtDH

RY/BY# tVCS VCC

Notes:

1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address.

2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.

Rev. A, Issue Date: 2005/01/07

EN29LV400AFigure 8. AC Waveforms for DATA# Polling During Embedded Algorithm

Operations

VA VA VA Addresses t t tCE# t

OE# tt

WE# t

Comple-True Complement Valid Data DQ[7] ment

Status True DQ[6:0] Status Data Valid Data Data t

RY/BY#

RCACCCHCEOEOEHDFOHBUSYNotes:

1. VA=Valid Address for reading Data# Polling status data

2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.

Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm

Operations

Addresses VA VA VA VA tRC

CE#

OE#

WE#

tCHACCtCEtOEtOEHtDFtOH

DQ6, DQ2

RY/BY#

Valid StatustBUSY(first read) Valid Status(second d)Valid Status(stops toggling) Valid Data This Data Sheet may be revised by subsequent versions ©2005 Eon Silicon Solution, Inc., www.essi.com.tw 33or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400A

Figure 10. Alternate CE# Controlled Write Operation Timings

PA for Program

0x555 for Program SA for Sector Erase

0x2AA for Erase 0x555 for Chip Erase

Addresses VA tWCtAStAH

WE# tWHtGHEL

OE# tCPtCPHtCWHWH1 / tCWHWH2 / tCWHWH3 tWS CE# tBUSYtDStDH

Data StatusDOUT PD for Program 0xA0 for 0x30 for Sector Erase Program 0x10 for Chip Erase

RY/BY#

tRH

Reset#

Notes:

PA = address of the memory location to be programmed. PD = data to be programmed at byte address. VA = Valid Address for reading program or erase status Dout = array data read at VA Shown above are the last two cycles of the program or erase command sequence and the last status read cycle Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence. WE# DQ6 DQ2

Figure 11. DQ2 vs. DQ6 Enter Embedded Erase Erase SuspendEnter Erase Suspend Program Enter Suspend ProgramErase Resume Erase Enter Suspend Read Erase Suspend Read Erase Erase CompleteThis Data Sheet may be revised by subsequent versions ©2005 Eon Silicon Solution, Inc., www.essi.com.tw 34or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400AFigure 12. Sector Protect/Unprotect Timing Diagram VID Vcc RESET# 0V 0V

tVIDRtVIDR SA,

ValidValidValid A6,A1,A0

Data 60h 60h 40h Status Sector Protect/UnprotectVerify CE#

>0.4µS

WE# >1µS Sector Protect: 150 uS Sector Unprotect: 15 mS

OE#

Notes:

Use standard microprocessor timings for this device for read and write cycles.

For Sector Protect, use A6=0, A1=1, A0=0. For Sector Unprotect, use A6=1, A1=1, A0=0.

Temporary Sector Unprotect

Parameter

Std tVIDRtRSP

Speed Option Unit

Description -45R-55R-70 -90 VID Rise and Fall Time

RESET# Setup Time for Temporary

Sector Unprotect

MinMin

500 4

µs

Figure 13. Temporary Sector Unprotect Timing Diagram

VID RESET#

0 or 3 V

CE#

0 or 3 V tVIDRtVIDR

WE#

RY/BY#

Rev. A, Issue Date: 2005/01/07

EN29LV400A

FIGURE 14. TSOP 12mm x 20mm

Rev. A, Issue Date: 2005/01/07

EN29LV400A

Rev. A, Issue Date: 2005/01/07

EN29LV400AFIGURE 15. FBGA 6mm x 8mm This Data Sheet may be revised by subsequent versions ©2005 Eon Silicon Solution, Inc., www.essi.com.tw 38or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400AABSOLUTE MAXIMUM RATINGS

Storage Temperature Plastic Packages

Ambient Temperature

With Power Applied

-65 to +125 -65 to +125 -55 to +125

°C °C °C

Parameter Value Unit

Output Short Circuit Current1

A9, OE#, Reset# 2

Voltage with

Respect to Ground

All other pins 3

200 mA -0.5 to +11.5 -0.5 to Vcc+0.5

V V

Vcc -0.5 to +4.0 V

Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC input voltage on A9, OE#, RESET# pins is –0.5V. During voltage transitions, A9, OE#, RESET# pins may

undershoot Vss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns.

3. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for

periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.

4. Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress

rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability.

RECOMMENDED OPERATING RANGES1

Ambient Operating Temperature Commercial Devices Industrial Devices Operating Supply Voltage Vcc

Parameter Value Unit

0 to 70 -40 to 85 Regulated Voltage Range: 3.0-3.6 Standard Voltage Range:

2.7 to 3.6

°C

Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.

Vcc+1.5V

Maximum Negative Overshoot

Waveform

Maximum Positive Overshoot Waveform

or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2005/01/07

EN29LV400AORDERING INFORMATION

EN29LV400A

T 󰄷 70

PACKAGING CONTENT (Blank) = Conventional P = Pb Free

TEMPERATURE RANGE

C=Commercial(0°C to +70°C) I = Industrial (-40°C to +85°C)

PACKAGE

T = 48-pin TSOP

B = 48-ball Fine Pitch Ball Grid Array (FBGA)

0.80mm pitch, 6mm x 8mm package

SPEED

45R = 45ns Regulated range 3.0V~3.6V

55R = 55ns Regulated range 3.0V~3.6V 70 = 70ns 90 = 90ns BOOT CODE SECTOR ARCHITECTURE T = Top Sector

B = Bottom Sector

BASE PART NUMBER

EN = Eon Silicon Solution Inc. 29LV = FLASH, 3V Read Program Erase 400 = 4 Megabit (512K x 8 / 256K x 16)

A = Version Identifier

Rev. A, Issue Date: 2005/01/07

EN29LV400ARevisions List

Revision No Description A

Initial Release

Date 2004/01/07

Rev. A, Issue Date: 2005/01/07

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EN29LV400A