MT40A2G8NRE-083E_B

MT40A4G4 – 128 Meg x 4 x 16 Banks x 2 RanksMT40A2G8 – 64 Meg x 8 x 16 Banks x 2 RanksDescription

The 16Gb (TwinDie™) DDR4 SDRAM uses

Micron’s 8Gb DDR4 SDRAM die (essentially two ranksof the 8Gb DDR4 SDRAM). Refer to Micron’s 8Gb

DDR4 SDRAM data sheet for the specifications not in-cluded in this document. Specifications for base partnumber MT40A2G4 correlate to TwinDie manufactur-ing part number MT40A4G4; specifications for basepart number MT40A1G8 correlate to TwinDie manu-facturing part number MT40A2G8.

Options

•Configuration

–128 Meg x 4 x 16 banks x 2 ranks–64 Meg x 8 x 16 banks x 2 ranks•FBGA package (Pb-free)–78-ball FBGA

(9.5mm x 13mm x 1.2mm) Die Rev :A–78-ball FBGA

(8.0mm x 12mm x 1.2mm) Die Rev :B•Timing – cycle time1

–0.750ns @ CL = 18 (DDR4-2666)–0.833ns @ CL = 16 (DDR4-2400)–0.833ns @ CL = 17 (DDR4-2400)–0.937ns @ CL = 15 (DDR4-2133)–0.937ns @ CL = 16 (DDR4-2133)•Self refresh–Standard

•Operating temperature

–Commercial (0°C ≤ TC ≤ 95°C)•Revision

Note:

1.CL = CAS (READ) latency.

Marking

4G42G8FSENRE-075E-083E-083-093E-093NoneNone:A:B

Features

•Uses 8Gb Micron die

•Two ranks (includes dual CS#, ODT, and CKE balls)•Each rank has 4 groups of 4 internal banks for con-current operation

•VDD = VDDQ = 1.2V (1.14–1.26V)•1.2V VDDQ-terminated I/O•JEDEC-standard ball-out•Low-profile package•TC of 0°C to 95°C

–0°C to 85°C: 8192 refresh cycles in 64ms–85°C to 95°C: 8192 refresh cycles in 32msTable 1: Key Timing Parameters

Speed Grade-075E-075-083E-083-093E-093Note:

1Data Rate(MT/s)266626662400240021332133Target tRCD-tRP-CL18-18-1819-19-1916-16-1617-17-1715-15-1516-16-16tRCD (ns)tRP (ns)CL (ns)13.5014.2513.3214.16 (13.75)14.06 (13.50)15.0013.5014.2513.3214.16 (13.75)14.06 (13.50)15.0013.5014.2513.3214.16 (13.75)14.06 (13.50)15.001.Refer to the Speed Bin Tables for additional details.

Table 2: Addressing

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以深圳市美光存储技术有限公司提供的参数为例，以下为MT40A2G8NRE-083E_B的详细参数，仅供参考

Ball Assignments and Descriptions

Figure 1: 78-Ball FBGA Ball Assignments (Top View)

1AVDDBVPPCVDDQDVSSQEVSSFVDDGVSSHVDDJVREFCAKVSSLRESET_nMVDDNVSSNotes:

23456789AVSSQVDDQDQ0NF, NF/TDQS_cNF, NF/DM_n/DBI_n/TDQS_tVSSQVDDQVSSVSSQBZQCDQS_cDQ1DQS_tVDDDQ3VDDQDVSSQEVSSFVDDGDQ4/NFDQ2DQ5/NFVDDQDQ6/NFDQ7/NFVDDQCK_cC2/ODT1ODTCK_tC0/CKE1CKECS_nC1/CS1_nRFU/TENHWE_n/A14ACT_nCAS_n/A15 RAS_n/A16A12/BC_nBG1VSSJVDDKVSSLALERT_nMBG0A10/APBA0A4A3BA1A6A0A1A5A8A2A9A7VPPNVDDA11PARA17/NCA131.See the FBGA 78-Ball Descriptions table.

2.Dark balls (with ring) designate balls that are specific to controlling the second die of

the TwinDie package when compared to a monolithic package.

3.A comma “,” separates the configuration; a slash “/” defines a selectable function. For

example: Ball A7 = NF, NF/DM_n/DBI_n/TDQS_t where NF applies to the x4 configurationonly. NF/DM_n/DBI_n/TDQS_t applies to the x8 configuration only and is selectable be-tween NF, DM_n, DBI_n, or TDQS_t via MRS.

Table 3: FBGA 78-Ball Descriptions

SymbolA[17:0]TypeInputDescriptionAddress inputs: Provide the row address for ACTIVATE commands and the col-umn address for READ/WRITE commands to select one location out of the memo-ry array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16, have additional functions; see individual entries in this table). The addressinputs also provide the op-code during the MODE REGISTER SET command. A16 isused on some 8Gb and 16Gb parts, and A17 is only used on some 16Gb parts.Auto precharge: A10 is sampled during READ and WRITE commands to deter-mine whether auto precharge should be performed to the accessed bank after aREAD or WRITE operation (HIGH = auto precharge; LOW = no auto precharge).A10 is sampled during a PRECHARGE command to determine whether the PRE-CHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only onebank is to be precharged, the bank is selected by the bank group and bank ad-dresses.Burst chop: A12/BC_n is sampled during READ and WRITE commands to deter-mine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW =burst-chopped). See the Command Truth Table.Command input: ACT_n indicates an ACTIVATE command. When ACT_n (alongwith CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are trea-ted as row address inputs for the ACTIVATE command. When ACT_n is HIGH(along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals.See the Command Truth Table.Bank address inputs: Define the bank (within a bank group) to which an ACTI-VATE, READ, WRITE, or PRECHARGE command is being applied. Also determineswhich mode register is to be accessed during a MODE REGISTER SET command.Bank group address inputs: Define the bank group to which an ACTIVATE,READ, WRITE, or PRECHARGE command is being applied. Also determines whichmode register is to be accessed during a MODE REGISTER SET command. BG[1:0]are used in the x4 and x8 configurations.Stack address inputs: These inputs are used only when devices are stacked;that is, 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are notused in the x16 configuration). DDR4 will support a traditional dual-die package(DDP), which uses these three signals for control of the second die (CS1_n, CKE1,ODT1). DDR4 is not expected to support a traditional quad-die package (QDP).For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave) type of configuration where C0, C1, and C2 are used as chipID selects in conjunction with a single CS_n, CKE, and ODT.Clock: Differential clock inputs. All address, command, and control input signalsare sampled on the crossing of the positive edge of CK_t and the negative edgeof CK_c.A10/APInputA12/BC_nInputACT_nInputBA[1:0]InputBG[1:0]InputC0/CKE1,C1/CS1_n,C2/ODT1InputCK_t,CK_cInput