•Single Voltage, Range 3V to 3.6V Supply•3-volt Only Read and Write Operation•Software Protected Programming•Fast Read Access Time – 100 ns•
Low Power Dissipation–15 mA Active Current
–40 µA CMOS Standby Current•
Sector Program Operation
–Single Cycle Reprogram (Erase and Program)–1024 Sectors (256 Bytes/Sector)
–Internal Address and Data Latches for 256 Bytes•Two 8K Bytes Boot Blocks with Lockout•Fast Sector Program Cycle Time – 20 ms•Internal Program Control and Timer
•DATA Polling for End of Program Detection •Typical Endurance > 10,000 Cycles
•CMOS and TTL Compatible Inputs and Outputs•Commercial and Industrial Temperature Ranges •
Green (Pb/Halide-free) Packaging Option
1.Description
The AT29LV020 is a 3-volt-only in-system Flash programmable and erasable read only memory (PEROM). Its 2 megabits of memory is organized as 262,144 bytes by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 100 ns with power dissipation of just 54 mW over the commer-cial temperature range. When the device is deselected, the CMOS standby current is less than 40 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29LV020 does not require high input voltages for programming. Five-volt-only commands determine the opera-tion of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29LV020 is performed on a sector basis; 256 bytes of data are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 256 bytes of data are captured at microprocessor speed and internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automati-cally erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin.
2-megabit (256K x 8) 3-volt Only Flash MemoryAT29LV020 0565D–FLASH–2/052.Pin Configurations
Pin NameA0 - A17CEOEWEI/O0 - I/O7NC
FunctionAddressesChip EnableOutput EnableWrite EnableData Inputs/OutputsNo Connect
2.132-lead PLCC Top View
A12A15A16NCVCCWEA172.232-lead TSOP (Type 1) Top View
I/O1I/O2GNDI/O3I/O4I/O5I/O614151617181920A7A6A5A4A3A2A1A0I/O056789101112134321323130292827262524232221A14A13A8A9A11OEA10CEI/O7A11A9A8A13A14A17WEVCCNCA16A15A12A7A6A5A41234567891011121314151632313029282726252423222120191817OEA10CEI/O7I/O6I/O5I/O4I/O3GNDI/O2I/O1I/O0A0A1A2A3 2
AT29LV020
0565D–FLASH–2/05
AT29LV0203.Block Diagram
4.Device Operation
4.1
Read
The AT29LV020 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line con-trol gives designers flexibility in preventing bus contention.
4.2Software Data Protection Programming
The AT29LV020 has 1024 individual sectors, each 256 bytes. Using the software data protec-tion feature, byte loads are used to enter the 256 bytes of a sector to be programmed. The AT29LV020 can only be programmed or reprogrammed using the software data protection fea-ture. The device is programmed on a sector basis. If a byte of data within the sector is to be changed, data for the entire 256-byte sector must be loaded into the device. The AT29LV020 automatically does a sector erase prior to loading the data into the sector. An erase command is not required.
Software data protection protects the device from inadvertent programming. A series of three program commands to specific addresses with specific data must be presented to the device before programming may occur. The same three program commands must begin each program operation. All software program commands must obey the sector program timing specifications. Power transitions will not reset the software data protection feature, however the software fea-ture will guard against inadvertent program cycles during power transitions.
Any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, a read opera-tion will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.The 256 bytes of data must be loaded into each sector. Any byte that is not loaded during the programming of its sector will be erased to read FFH. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After
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the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE (or CE) within 150 µs of the low to high transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 150 µs of the last low to high transition, the load period will end and the internal programming period will start. A8 to A17 specify the sector address. The sector address must be valid during each high to low transition of WE (or CE). A0 to A7 specify the byte address within the sector. The bytes may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.
4.3Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29LV020 in the following ways: (a) VCC sense – if VCC is below 1.8V (typical), the program function is inhibited; (b) VCCpower on delay – once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming; (c) Program inhibit – holding any one of OE low, CEhigh or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.4.4Input Levels
While operating with a 3.3V ± 10% power supply, the address inputs and control inputs (OE, CEand WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can be driven from 0 to 3.6V.
4.5Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part (i.e., using the device code), and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4-megabit densities and, with each density’s sector size in a memory map, have the system soft-ware apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.
4.6DATA PollingThe AT29LV020 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.4.7Toggle Bit
In addition to DATA polling the AT29LV020 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
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AT29LV020
0565D–FLASH–2/05
AT29LV0204.8
Optional Chip Erase Mode
The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.
4.9Boot Block Programming Lockout
The AT29LV020 has two designated memory blocks that have a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. Each of these blocks consists of 8K bytes; the programming lockout feature can be set independently for either block. While the lockout feature does not have to be activated, it can be activated for either or both blocks.
These two 8K memory sections are referred to as boot blocks. Secure code which will bring up a system can be contained in a boot block. The AT29LV020 blocks are located in the first 8K bytes of memory and the last 8K bytes of memory. The boot block programming lockout feature can therefore support systems that boot from the lower addresses of memory or the higher addresses. Once the programming lockout feature has been activated, the data in that block can no longer be erased or programmed; data in other memory locations can still be changed through the regular programming methods. To activate the lockout feature, a series of seven program commands to specific addresses with specific data must be performed. Please see Boot Block Lockout Feature Enable Algorithm.
If the boot block lockout feature has been activated on either block, the chip erase function will be disabled.
4.9.1
Boot Block Lockout Detection
A software method is available to determine whether programming of either boot block section is locked out. See Software Product Identification Entry and Exit sections. When the device is in the software product identification mode, a read from location 00002H will show if programming the lower address boot block is locked out while reading location 3FFF2H will do so for the upper boot block. If the data is FE, the corresponding block can be programmed; if the data is FF, the program lockout feature has been activated and the corresponding block cannot be pro-grammed. The software product identification exit mode should be used to return to standard operation.
5.Absolute Maximum Ratings*
Temperature Under Bias................................-55°C to +125°CStorage Temperature.....................................-65°C to +150°CAll Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25VAll Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6VVoltage on A9 (including NC Pins)
with Respect to Ground...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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6.DC and AC Operating Range
AT29LV020-10
Operating
Temperature (Case)VCC Power Supply(1)Notes:
Com.Ind.
0°C - 70°C-40°C - 85°C3.3V ± 0.3V
AT29LV020-120°C - 70°C-40°C - 85°C3.3V ± 0.3V
AT29LV020-200°C - 70°C-40°C - 85°C3.3V ± 0.3V
AT29LV020-250°C - 70°C-40°C - 85°C3.3V ± 0.3V
1.After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an opera-tional mode is started.2.
Not recommended for New Designs.
7.Operating Modes
ModeReadProgram(2)
Standby/Write InhibitProgram InhibitProgram InhibitOutput DisableProduct Identification Hardware
VIL
VIL
VIH
A1 - A17 = VIL, A9 = VH(3), A0 = VILA1 - A17 = VIL, A9 = VH(3), A0 = VIH
A0 = VILA0 = VIH
Manufacturer Code(4)
Device Code(4)Manufacturer Code(4)
Device Code(4)
CEVILVILVIHXXX
OEVILVIH X(1)XVILVIH
WEVIHVILXVIHXX
AiAi
I/O DOUT
AiDIN
XHighZ
HighZ
SoftwareNotes:
(5)
1.X can be VIL or VIH.
2.Refer to AC Programming Waveforms.3.VH = 12.0V ± 0.5V.
4.Manufacturer Code: 1F, Device Code: BA.
5.See details under Software Product Identification Entry/Exit.
8.DC Characteristics
SymbolILIILOISB1ISB2ICCVILVIHVOLVOH
ParameterInput Load CurrentOutput Leakage CurrentVCC Standby Current CMOSVCC Standby Current TTLVCC Active CurrentInput Low VoltageInput High VoltageOutput Low VoltageOutput High Voltage
IOL = 1.6 mA; VCC = 3.0VIOH = -100 µA; VCC = 3.0V
2.42.0
0.45
ConditionVIN = 0V to VCCVI/O = 0V to VCC
CE = VCC - 0.3V to VCCCE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA; VCC = 3.6V
Com.Ind.
Min
Max1140501150.6
UnitsµAµAµAµAmAmAVVVV
6
AT29LV020
0565D–FLASH–2/05
AT29LV0209.AC Read Characteristics
AT29LV020-10
SymboltACCtCE(1)tOE(2)tDF(3)(4)tOHNote:
Parameter
Address to Output DelayCE to Output DelayOE to Output DelayCE or OE to Output FloatOutput Hold from OE, CE or Address, Whichever Occurred First
000Min
Max1001004025
000
AT29LV020-12Min
Max1201205030
000
AT29LV020-20Min
Max20020010050
000
AT29LV020-25Min
Max25025012060
Unitsnsnsnsnsns
Not recommended for New Designs.
10.AC Read Waveforms(1)(2)(3)(4)
Notes:
1.CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2.OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.3.tDF is specified from OE or CE whichever occurs first (CL = 5 pF).4.This parameter is characterized and is not 100% tested.
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0565D–FLASH–2/05
11.Input Test Waveforms and Measurement Level
tR, tF < 5 ns12.Output Test Load
13.Pin Capacitance
f = 1 MHz, T = 25°C(1)
SymbolCINCOUTNote:
Typ48
Max612
UnitspFpF
ConditionsVIN = 0VVOUT = 0V
1.These parameters are characterized and not 100% tested.
8
AT29LV020
0565D–FLASH–2/05
AT29LV02014.AC Byte Load Characteristics
SymboltAS, tOEStAHtCStCHtWPtDStDH, tOEHtWPH
Parameter
Address, OE Set-up TimeAddress Hold TimeChip Select Set-up TimeChip Select Hold TimeWrite Pulse Width (WE or CE)Data Set-up TimeData, OE Hold TimeWrite Pulse Width High
Min101000020010010200
Max
Unitsnsnsnsnsnsnsnsns
15.AC Byte Load Waveforms(1)(2)
15.1
WE Controlled15.2CE ControlledNotes:1.The software data protection commands must be applied prior to byte loads.
2.A complete sector (256 bytes) should be loaded using these waveforms as shown in the Software Protected Byte Load
waveforms (see next page).
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0565D–FLASH–2/05
16.Program Cycle Characteristics
SymboltWCtAStAHtDStDHtWPtBLCtWPH
ParameterWrite Cycle TimeAddress Set-up TimeAddress Hold TimeData Set-up TimeData Hold TimeWrite Pulse Width Byte Load Cycle TimeWrite Pulse Width High
2001010010010200
150
Min
Max20
Unitsmsnsnsnsnsnsµsns
17.Software Protected Program Waveform
Notes:
1.A8 through A17 must specify the sector address during each high to low transition of WE (or CE) after the software code has been entered.2.OE must be high when WE and CE are both low.3.All words that are not loaded within the sector being programmed will be indeterminate.
18.Programming Algorithm(1)
LOAD DATA AATOADDRESS 5555LOAD DATA 55TOADDRESS 2AAALOAD DATA A0TOADDRESS 5555WRITES ENABLEDNotes:
1.Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2.Data Protect state will be re-activated at end of
program cycle.
LOAD DATATOSECTOR (256 BYTES)(3)ENTER DATAPROTECT STATE(2)3.256 bytes of data MUST BE loaded.
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AT29LV020
0565D–FLASH–2/05
AT29LV02019.Data Polling Characteristics(1)
SymboltDHtOEHtOEtWRNotes:
ParameterData Hold TimeOE Hold TimeOE to Output Delay(2)Write Recovery Time
1.These parameters are characterized and not 100% tested.2.See tOE spec in AC Read Characteristics.
0Min1010
Typ
Max
Unitsnsnsnsns
20.Data Polling Waveforms
21.Toggle Bit Characteristics(1)
SymboltDHtOEHtOEtOEHPtWRNotes:
ParameterData Hold TimeOE Hold TimeOE to Output Delay(2)OE High PulseWrite Recovery Time
1.These parameters are characterized and not 100% tested.2.See tOE spec in AC Read Characteristics.
1500Min1010
Typ
Max
Unitsnsnsnsnsns
22.Toggle Bit Waveforms(1)(3)
Notes:1.Toggling either OE or CE or both OE and CE will operate toggle bit.2.Beginning and ending state of I/O6 will vary.
3.Any address location may be used but the address should not vary.
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0565D–FLASH–2/05
23.Software Product Identification
Entry(1)
LOAD DATA AATOADDRESS 555525.Boot Block Lockout
Feature Enable Algorithm(1)
LOAD DATA AATOADDRESS 5555LOAD DATA 55TOADDRESS 2AAALOAD DATA 55TOADDRESS 2AAALOAD DATA 90TOADDRESS 5555LOAD DATA 80TOADDRESS 5555PAUSE 20 mSENTER PRODUCTIDENTIFICATIONMODE(2)(3)(5)LOAD DATA AATOADDRESS 555524.Software Product Identification
Exit(1)
LOAD DATA AATOADDRESS 5555LOAD DATA 55TOADDRESS 2AAALOAD DATA 40TOADDRESS 5555LOAD DATA 55TOADDRESS 2AAALOAD DATA 00TOADDRESS 00000H(2)LOAD DATA FFTOADDRESS 3FFFFH(3)LOAD DATA F0TOADDRESS 5555PAUSE 20 mSPAUSE 20 mSNotes:
PAUSE 20 mSEXIT PRODUCTIDENTIFICATIONMODE(4)1.Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2.Lockout feature set on lower address boot block.3.Lockout feature set on higher address boot block.
Notes:
1.Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).2.A1 - A17 = VIL.
Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH.
3.The device does not remain in identification mode if
powered down.4.The device returns to standard operation mode.5.Manufacturer Code is 1F. The Device Code is BA.
12
AT29LV020
0565D–FLASH–2/05
AT29LV02026.Ordering Information
26.1
Standard Package
ICC (mA)Active15
100
1515
120
1515
200
1515
250
15
0.050.050.040.050.040.050.04Standby0.04
Ordering CodeAT29LV020-10JCAT29LV020-10TCAT29LV020-10JIAT29LV020-10TIAT29LV020-12JCAT29LV020-12TCAT29LV020-12JIAT29LV020-12TIAT29LV020-20JCAT29LV020-20TCAT29LV020-20JIAT29LV020-20TIAT29LV020-25JCAT29LV020-25TCAT29LV020-25JIAT29LV020-25TI
Package32J32T32J32T32J32T32J32T32J32T32J32T32J32T32J32T
Operation RangeCommercial(0° to 70°C)Industrial(-40° to 85°C)Commercial(0° to 70°C)Industrial(-40° to 85°C)Commercial(0° to 70°C)Industrial(-40° to 85°C)Commercial(0° to 70°C)Industrial(-40° to 85°C)
tACC(ns)
Note:
Not recommended for New Designs.
26.2Green Package Option (Pb/Halide-free)
ICC (mA)Active15
Standby0.05
Ordering CodeAT29LV020-10JUAT29LV020-10TU
Package32J32T
Operation RangeIndustrial(-40° to 85°C)
tACC(ns)100
Package Type
32J32T
32-lead, Plastic J-leaded Chip Carrier (PLCC)32-lead, Thin Small Outline Package (TSOP)
13
0565D–FLASH–2/05
27.Packaging Information
27.1
32J – PLCC
1.14(0.045) X 45˚PIN NO. 1IDENTIFIER1.14(0.045) X 45˚0.318(0.0125)0.191(0.0075)BE1EB1E2 eD1D AA2A10.51(0.020)MAX45˚ MAX (3X)COMMON DIMENSIONS(Unit of Measure = mm)SYMBOLD2MIN3.1751.524 0.38112.31911.3549.90614.85913.89412.4710.6600.330NOM–––––––––––1.270 TYPMAX3.5562.413–12.57311.50610.92215.11314.04613.4870.813 0.533NOTEAA1A2DD1D2 Note 2Notes:1.This package conforms to JEDEC reference MS-016, Variation AE. 2.Dimensions D1 and E1 do not include mold protrusion.Allowable protrusion is .010\"(0.254 mm) per side. Dimension D1and E1 include mold mismatch and are measured at the extremematerial condition at the upper or lower parting line.3. Lead coplanarity is 0.004\" (0.102 mm) maximum.EE1 E2BB1eNote 210/04/01 2325 Orchard Parkway San Jose, CA 95131TITLE32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO.32JREV. BR 14
AT29LV020
0565D–FLASH–2/05
AT29LV02027.2
32T – TSOP
PIN 10º ~ 8º cPin 1 IdentifierD1DLebA2L1EASEATING PLANEGAGE PLANEA1SYMBOLAA1A2Notes:1.This package conforms to JEDEC reference MO-142, Variation BD. 2.Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.3. Lead coplanarity is 0.10 mm maximum.DD1EL L1bceCOMMON DIMENSIONS(Unit of Measure = mm)MIN–0.050.9519.8018.307.900.50NOM––1.0020.0018.408.000.600.25 BASIC0.170.100.22–0.50 BASIC0.27 0.21MAX1.200.151.0520.2018.508.100.70Note 2Note 2 NOTE10/18/01 2325 Orchard Parkway San Jose, CA 95131TITLE32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP)DRAWING NO.32TREV. BR 15
0565D–FLASH–2/05
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