CY22801
Universal Programmable Clock
Generator (UPCG)
Features
•Integrated phase-locked loop (PLL)•Field programmable•Input frequency range:—Crystal: 8–30 MHz —CLKIN: 1–133 MHz•Output frequency:
—LVCMOS: 1–200 MHz
•Low jitter, high accuracy outputs•3.3V operation
•8-pin SOIC package
Benefits
•Inventory of only one device, CY22801, is needed to use in various applications
•In-house programming of samples and prototype quantities is available using the CY36800 InstaClock Kit
•Can customize the input and output frequencies to suit your needs
•High-performance PLL tailored for multiple applications•Meets critical timing requirements in complex system designs
•Enables application compatibility
Logic Block DiagramPin ConfigurationCY228018-pin SOICXIN/CLKINVDDNCVSS12348765XOUTCLKCCLKACLKBXIN/CLKINXTALOSCCLKAPLLOUTPUTDIVIDERSCLKBCLKCXOUTPin Description
NameXINVDDNCVSSCLKBCLKACLKCXOUT
Pin Number
12345678
Description
Reference Input: Crystal or External Clock3.3V Voltage Supply
No Connect; leave this pin floatingGroundClock Output BClock Output AClock Output C
Reference Output: Connect to external crystal. When the reference is an external clock signal, this pin is not used and must be left floating.
CypressSemiconductorCorporationDocument #: 001-15571 Rev. **
•198 Champion Court•
SanJose,CA95134-1709•408-943-2600
Revised May 10, 2007
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General Description
The CY22801 is a flash-programmable clock generator thatsupports various applications in consumer and communica-tions markets. The device uses a Cypress proprietary PLL todrive up to three configurable outputs in an 8-pin SOIC.The CY22801 can be programmed with an easy-to-useprogrammer dongle, the CY36800, in conjunction with theCyClocksRT™ software. This enables fast sample generationof prototype builds for user-defined frequencies.
Field Programming the CY22801
The CY22801 is programmed using the CY36800 USBprogrammer dongle. The CY22801 is flash-technology based,so the parts can be reprogrammed up to 100 times. Thisenables fast and easy design changes and product updates,and eliminates any issues with old and out-of-date inventory.Samples and small prototype quantities can be programmedusing the CY36800 programmer. Cypress’s value added distri-bution partners and third party programming systems from BPMicrosystems, HiLo Systems, and others, are available forlarge production quantities.
CyClocksRT Software
CyClocksRT is an easy-to-use software application thatenables the user to custom-configure the CY22801. Users canspecify the XIN/CLKIN frequency, crystal load capacitance,and output frequencies. CyClocksRT then creates anindustry-standard JEDEC file, which is used to program theCY22801.
When needed, an advanced mode is available that enablesusers to override the automatically generated VCO frequencyand output divider values.
CyClocksRT is a component of the CyberClocks™ software,which can be downloaded free of charge from the Cypresswebsite at http://www.cypress.com.
CY36800 InstaClock™ Kit
The Cypress CY36800 InstaClock Kit comes with everythingneeded to design the CY22801 and program samples andsmall prototype quantities. The CyClocksRT software is usedto quickly create a JEDEC programming file, which is thendownloaded directly to the portable programmer that isincluded in the CY36800 InstaClock Kit. The JEDEC file canalso be saved for use in a production programming system forlarger volumes.
The CY36800 also comes with five samples of the CY22800,which can be programmed with preconfigured JEDEC filesusing the InstaClock software.
Output Clock Frequencies
The CY22801 is a very flexible clock generator with up to threeindividual outputs, generated from an integrated PLL. Detailsare shown in Figure1.
Document #: 001-15571 Rev. **CY22801
The output of the PLL runs at high frequency and is divideddown to generate the output clocks. Two programmabledividers are available for this purpose. Thus, although theoutput clocks may be different frequencies, they must berelated, based on the PLL frequency.
It is also possible to direct the reference clock input to any ofthe outputs, thereby bypassing the PLL. Lastly, the referenceclock may be passed through either divider.
Figure 1. Basic PLL Block Diagram
PostREFDivider(XIN/CLKIN)/QPFDVCO1NCLKA/PCrosspointCLKBPostSwitchDividerMatrixCLKC2NReference Crystal Input
The input crystal oscillator of the CY22801 is an importantfeature because of the flexibility it allows the user in selectinga crystal as a reference clock source. The oscillator inverterhas programmable gain, enabling maximum compatibility witha reference crystal, based on manufacturer, process, perfor-mance, and quality.
Input load capacitors are placed on the CY22801 die to reduceexternal component cost. These capacitors are trueparallel-plate capacitors, designed to reduce the frequencyshift that occurs when nonlinear load capacitance is affectedby load, bias, supply, and temperature changes.
The value of the input load capacitors is determined by eightbits in a programmable register. Total load capacitance isdetermined by the formula:
CapLoad = (CL – CBRD – CCHIP)/0.09375 pF
In CyClocksRT, enter the crystal capacitance (CL). The valueof CapLoad will be determined automatically and programmedinto the CY22801.
Applications
Controlling Jitter
Jitter is defined in many ways, including: •Phase noise•Long-term jitter•Cycle-to-cycle jitter•Period jitter•Absolute jitter
•Deterministic jitter
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CY22801
These jitter terms are usually given in terms of RMS,peak-to-peak, or in the case of phase noise, dBC/Hz withrespect to the fundamental frequency. Actual jitter isdependent on
•XIN jitter and edge rate•Number of active outputs•Output frequencies•Supply voltage•Temperature•Output load
Power supply noise and clock output loading are two majorsystem sources of clock jitter. Power supply noise can bemitigated by proper power supply decoupling (0.1-μF ceramiccap) of the clock and ensuring a low impedance ground to thechip. Reducing capacitive clock output loading to a minimumTable 1.Cypress Programmable Clocks[1]
Part #CY22800CY22801CY22050CY22150CY25100CY25200CY241V08CY22392CY22381CY22393CY22394/5CY22388/89/91
No. of PLL
111111133334
Input Freq.0.5–1001–1331–1331–1338–1663–16627/13.51–1661–1661–1661–1661–100
Output Freq.1–2001–2000.08–2000.08–2003–2003–20027/13.51–2001–2001–2001–2004.2–166
lowers current spikes on the clock edges and thus reducesjitter.
Reducing the total number of active outputs also reduces jitterin a linear fashion. However, it is better to use two outputs todrive two loads than one output to drive two loads.
For additional information, refer to the application note, Jitterin PLL-based Systems: Causes, Effects, and Solutions,available at http://www.cypress.com.
Cypress Programmable Clocks
Cypress offers a wide range of programmable clock synthe-sizers that can generate any other frequencies not covered bythe CY22801. Table1 summarizes all Cypress programmabledevices including CY22801.
Package8-SOIC8-SOIC16-TSSOP16-TSSOP8-SOIC/TSSOP16-TSSOP8-SOIC16-TSSOP8-SOIC16-TSSOP16-TSSOP16/20-TSSOP,32-QFN
No. of Outputsup to 3up to 3up to 6up to 6up to 2up to 6up to 2up to 6up to 3up to 6up to 5up to 8
Spread SpectrumYesNoNoNoYesYesNoNoNoNoNoNo
VCXOYesNoNoNoNoNoYesNoNoNoNoYes
I2CNoNoNoYesNoNoNoNoNoYesNoNo
Note
1.The CY22800 and CY22801 are programmed using the programming dongle included in the CY36800 InstaClock Kit. The CY3672 programmer can be used to
program all other Cypress Programmable Clocks.
Document #: 001-15571 Rev. **Page 3 of 7
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CY22801
Absolute Maximum Conditions
ParameterVDDTSTJVIOESD
Supply VoltageStorage TemperatureJunction TemperatureInput and Output Voltage
Electro-Static Discharge Voltage per MIL-STD-833, Method 3015
Description
Min–0.5–65–VSS – 0.52000
Max4.6150125VDD + 0.5
–
UnitV°C°CVV
Recommended Operating Conditions
ParameterVDDTACLOADtPU
Operating VoltageAmbient Temperature
Max. Load Capacitance on the CLK output
Power up time for VDD to reach minimum specified voltage (power ramps must be monotonic)
Description
Min3.140–0.05
Typ3.3–––
Max3.477015500
UnitV°CpFms
Recommended Crystal Specifications
ParameterFNOMCLNOMR1DL
Name
Nominal Crystal FrequencyNominal Load Capacitance
Equivalent Series Resistance Fundamental mode(ESR)
Crystal Drive Level
No external series resistor assumed
Description
Parallel resonance, fundamental mode, and AT cut
Min86––
Typ––350.5
Max3030502
UnitMHzpFΩmW
DC Electrical Specifications[2]
ParameterIOHIOLVIHVILCIN1CIN2IDD[3, 4]Name
Output High CurrentOutput Low CurrentInput High VoltageInput Low VoltageInput CapacitanceInput CapacitanceVDD Supply Current
All input pins except XIN and XOUTXIN and XOUT pins
Description
VOH = VDD – 0.5, VDD = 3.3V (source)VOL = 0.5, VDD = 3.3V (sink)
Min12120.7*VDDVSS – 0.3
–––
Typ2424–––2470
Max––VDD + 0.30.3*VDD
7––
UnitmAmAVVpFpFmA
Notes
2.Not 100% tested, guaranteed by design.
3.IDD current specified for three CLK outputs running at 100 MHz.
4.Use CyClocksRT™ to calculate actual IDD for specific output frequency configurations.
Document #: 001-15571 Rev. **Page 4 of 7
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CY22801
AC Electrical Characteristics[2]
ParameterfREFCfREFDfOUTDCt3t4t5
[5]Name
Reference Frequency - crystalReference Frequency - drivenOutput FrequencyOutput Duty CycleRising Edge Slew RateFalling Edge Slew RateSkewClock JitterPLL Lock Time
DescriptionMin811
Typ–––501.41.4–250–
Max3013320055––250–3
UnitMHzMHzMHz%V/nsV/nspspsms
Duty Cycle is defined in Figure3, 50% of VDDOutput Clock Rise Time, 20% - 80% of VDDOutput Clock Fall Time, 80% - 20% of VDDOutput-output skew between related outputsPeak-to-peak period jitter
450.80.8–––
t6[6]t10
Test Circuit
Figure 2. Test Circuit Diagram
VDD
0.1μF
OUTPUTS
CLKoutCLOAD
Timing Definitions
Figure 3. Duty Cycle Definition; DC = t2/t1
t1t2CLK50%50%GND
Figure 4. Rise and Fall Time Definitions
t380%CLK20%t4Notes
5.Skew value guaranteed when outputs are generated from the same divider bank.
6.Jitter measurement may vary. Actual jitter is dependent on input jitter and edge rate, number of active outputs, input and output frequencies, supply voltage, temperature, and output load. For more information, refer to the application note, Jitter in PLL-based Systems: Causes, Effects, and Solutions.
Document #: 001-15571 Rev. **Page 5 of 7
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CY22801
Ordering Information
Ordering CodeCY22801FXC
Package Type8-Pin SOIC
Operating RangeCommercial
Operating Voltage3.3V
Package Diagram
Figure 5. 8-Lead (150-Mil) SOIC S8
PIN1ID411.DIMENSIONSININCHES[MM]MIN.MAX.2.PIN1IDISOPTIONAL,ROUNDONSINGLELEADFRAMERECTANGULARONMATRIXLEADFRAME0.230[5.842]0.244[6.197]0.150[3.810]0.157[3.987]3.REFERENCEJEDECMS-0124.PACKAGEWEIGHT0.07gmsPART#S08.15STANDARDPKG.SZ08.15LEADFREEPKG.580.189[4.800]0.196[4.978]SEATINGPLANE0.010[0.254]0.016[0.406]X45°0.061[1.549]0.068[1.727]0.004[0.102]0.050[1.270]BSC0.004[0.102]0.0098[0.249]0°~8°0.016[0.406]0.035[0.889]0.0075[0.190]0.0098[0.249]0.0138[0.350]0.0192[0.487]51-85066-*CCyClocksRT, CyberClocks, and InstaClock are trademarks of Cypress Semiconductor Corporation. All products and companynames mentioned in this document may be the trademarks of their respective holders.
Document #: 001-15571 Rev. **Page 6 of 7
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to beused for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize itsproducts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypressproducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY22801
Document History Page
Document Title: CY22801 Universal Programmable Clock Generator (UPCG)Document Number: 001-15571REV.**
ECN NO.1058080
Issue DateSee ECN
Orig. of Change
KVM/New data sheetKKVTMP
Description of Change
Document #: 001-15571 Rev. **Page 7 of 7
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