H
High CMR, High Speed TTLCompatible OptocouplersTechnical Data
6N137HCNW137HCNW2601HCNW2611HCPL-0600HCPL-0601HCPL-0611HCPL-0630
HCPL-0631HCPL-0661HCPL-2601HCPL-2611HCPL-2630HCPL-2631HCPL-4661
Features
• 5 kV/µs Minimum CommonMode Rejection (CMR) atVCM= 50 V for HCPL-X601/X631, HCNW2601 and
10kV/µs Minimum CMR atVCM = 1000 V for HCPL-X611/X661, HCNW2611• High Speed: 10 MBd Typical• LSTTL/TTL Compatible• Low Input CurrentCapability: 5 mA
• Guaranteed ac and dc
Performance over Temper-ature: -40°C to +85°C• Available in 8-Pin DIP,
SOIC-8, Widebody Packages• Strobable Output (SingleChannel Products Only)• Safety Approval
UL Recognized - 2500 V rmsfor 1 minute and 5000Vrms*for 1 minute per UL1577CSA Approved
VDE 0884 Approved withVIORM= 630 V peakfor
HCPL-2611 Option 060 andVIORM=1414 V peak forHCNW137/26X1BSI Certified
(HCNW137/26X1 Only)• MIL-STD-1772 VersionAvailable (HCPL-56XX/66XX)
Applications
• Isolated Line Receiver• Computer-PeripheralInterfaces
• Microprocessor SystemInterfaces
• Digital Isolation for A/D,D/A Conversion
• Switching Power Supply• Instrument Input/OutputIsolation
• Ground Loop Elimination• Pulse TransformerReplacement
• Power Transistor Isolationin Motor Drives
• Isolation of High SpeedLogic Systems
Description
The 6N137, HCPL-26XX/06XX/4661, HCNW137/26X1 areoptically coupled gates thatcombine a GaAsP light emittingdiode and an integrated high gainphoto detector. An enable inputallows the detector to be strobed.The output of the detector IC is
Functional Diagram
6N137, HCPL-2601/2611HCPL-0600/0601/0611HCNW137/2601/2611NCANODECATHODENC1234SHIELD8765VCCVEVOGNDANODE 1CATHODE 1CATHODE 2ANODE 2HCPL-2630/2631/4661HCPL-0630/0631/06611234SHIELD8765VCCVO1VO2GNDTRUTH TABLE(POSITIVE LOGIC)LEDONOFFONOFFONOFFENABLEHHLLNCNCOUTPUTLHHHLHTRUTH TABLE(POSITIVE LOGIC)LEDONOFFOUTPUTLH*5000 V rms/1 Minute rating is for HCNW137/26X1 and Option 020 (6N137, HCPL-2601/11/30/31, HCPL-4661) products only.A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of thiscomponent to prevent damage and/or degradation which may be induced by ESD.
1-146
5965-3594E
元器件交易网www.cecb2b.com
an open collector Schottky-clamped transistor. The internalshield provides a guaranteedcommon mode transient
immunity specification of 5,000V/µs for the HCPL-X601/X631and HCNW2601, and 10,000 V/µsfor the HCPL-X611/X661 andHCNW2611.
This unique design providesmaximum ac and dc circuitisolation while achieving TTLcompatibility. The optocoupler acand dc operational parametersare guaranteed from -40°C to+85°C allowing troublefreesystem performance.
The 6N137, HCPL-26XX, HCPL-06XX, HCPL-4661, HCNW137,and HCNW26X1 are suitable forhigh speed logic interfacing,input/output buffering, as linereceivers in environments thatconventional line receiverscannot tolerate and are recom-mended for use in extremely highground or induced noiseenvironments.
Selection Guide
Minimum CMRInputOn-CurrentOutput(mA)Enable5YESNO5,00010,0001,0003, 5001,0001,000[2]1,000501,00050300501,0005012.53YESNOYESNOYESYESYESNOYESNO[3]8-Pin DIP (300 Mil)SingleChannelPackage6N137HCPL-2630HCPL-2601HCPL-2631HCPL-2611HCPL-4661HCPL-2602[1]HCPL-2612[1]HCPL-261A[1]HCPL-263A[1]HCPL-261N[1]HCPL-263N[1]DualChannelPackageSmall-Outline SO-8SingleChannelPackageHCPL-0600HCPL-0630HCPL-0601HCPL-0631HCPL-0611HCPL-0661DualChannelPackageWidebody(400 Mil)SingleChannelPackageHCNW137HCNW2601HCNW2611dV/dt(V/µs)NAVCM(V)NAHermeticSingleand DualChannelPackagesHCPL-061A[1]HCPL-063A[1]HCPL-061N[1]HCPL-063N[1]HCPL-193X[1]HCPL-56XX[1]HCPL-66XX[1]Notes:
1. Technical data are on separate HP publications.
2. 15 kV/µs with VCM = 1 kV can be achieved using HP application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
1-147
元器件交易网www.cecb2b.com
Ordering Information
Specify Part Number followed by Option Number (if desired).Example:
HCPL-2611#XXX
020 = 5000 V rms/1 minute UL Rating Option*060 = VDE 0884 VIORM = 630 Vpeak Option**300 = Gull Wing Surface Mount Option†500 = Tape and Reel Packaging Option
Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor forinformation.
*For 6N137, HCPL-2601/11/30/31 and HCPL-4661 (8-pin DIP products) only.
**For HCPL-2611 only. Combination of Option 020 and Option 060 is not available.†Gull wing surface mount option applies to through hole parts only.
Schematic
6N137, HCPL-2601/2611HCPL-0600/0601/0611HCNW137, HCNW2601/2611HCPL-2630/2631/4661HCPL-0630/0631/0661ICCICC8IO6VCCVOIF2+1+VF1–2IF18IO17VCCVO1VF–3SHIELDIE75GNDSHIELD3–VF2+4SHIELD5GNDIF2IO26VEVO2USE OF A 0.1 µF BYPASS CAPACITOR CONNECTEDBETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).1-148
元器件交易网www.cecb2b.com
Package Outline Drawings
8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)
9.65 ± 0.257.62 ± 0.25(0.380 ± 0.010)(0.300 ± 0.010)TYPE NUMBER8765OPTION CODE*6.35 ± 0.25(0.250 ± 0.010)HP XXXXZDATE CODEYYWWUL1234RECOGNITION1.19 (0.047) MAX.1.78 (0.070) MAX.5° TYP.0.254+ 0.076- 0.0514.70 (0.185) MAX.(0.010+ 0.003)- 0.002)0.51 (0.020) MIN.2.92 (0.115) MIN.1.080 ± 0.3200.65 (0.025) MAX.DIMENSIONS IN MILLIMETERS AND (INCHES).(0.043 ± 0.013)2.54 ± 0.25*MARKING CODE LETTER FOR OPTION NUMBERS\"L\" = OPTION 020RU(0.100 ± 0.010)\"V\" = OPTION 060OPTION NUMBERS 300 AND 500 NOT MARKED.**JEDEC Registered Data (for 6N137 only).
8-pin DIP Package with Gull Wing Surface Mount Option 300(6N137, HCPL-2601/11/30/31, HCPL-4661)
PAD LOCATION (FOR REFERENCE ONLY)9.65 ± 0.25(0.380 ± 0.010)1.016 (0.040)1.194 (0.047)8765(0.190)4.826TYP.6.350 ± 0.25(0.250 ± 0.010)9.398 (0.370)9.906 (0.390)12340.381 (0.015)1.194 (0.047)0.635 (0.025)1.778 (0.070)1.7809.65 ± 0.25(0.070)(0.380 ± 0.010)1.19MAX.(0.047)7.62 ± 0.25MAX.(0.300 ± 0.010)0.254+ 0.076- 0.051(0.165)4.19MAX.(0.010+ 0.003)- 0.002)1.080 ± 0.320(0.043 ± 0.013)0.635 ± 0.25(0.025 ± 0.010)2.540.635 ± 0.13012° NOM.(0.100)(0.025 ± 0.005)BSCDIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).1-149
元器件交易网www.cecb2b.com
Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61)
87653.937 ± 0.127(0.155 ± 0.005)XXXYWW5.842 ± 0.203(0.236 ± 0.008)TYPE NUMBER(LAST 3 DIGITS)DATE CODE12340.381 ± 0.076(0.016 ± 0.003)1.270BSG(0.050)5.080 ± 0.127(0.200 ± 0.005)7°0.432(0.017)45° X3.175 ± 0.127(0.125 ± 0.005)1.524(0.060)0.152 ± 0.051(0.006 ± 0.002)0.228 ± 0.025(0.009 ± 0.001)DIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).0.305MIN.(0.012)8-Pin Widebody DIP Package (HCNW137, HCNW2601/11)
11.15 ± 0.15(0.442 ± 0.006)876511.00MAX.(0.433)9.00 ± 0.15(0.354 ± 0.006)TYPE NUMBERDATE CODEHP HCNWXXXXYYWW12341.55(0.061)MAX.10.16 (0.400)TYP.7° TYP.+ 0.0760.254- 0.0051+ 0.003)(0.010- 0.002)5.10MAX.(0.201)3.10 (0.122)3.90 (0.154)2.54 (0.100)TYP.1.78 ± 0.15(0.070 ± 0.006)0.40 (0.016)0.56 (0.022)0.51 (0.021) MIN.DIMENSIONS IN MILLIMETERS (INCHES).1-150
元器件交易网www.cecb2b.com
8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300(HCNW137, HCNW2601/11)
11.15 ± 0.15(0.442 ± 0.006)PAD LOCATION (FOR REFERENCE ONLY)8765(0.242)6.15TYP.9.00 ± 0.15(0.354 ± 0.006)12.30 ± 0.30(0.484 ± 0.012)12341.30.9(0.051)(0.035)1.5512.30 ± 0.30(0.061)(0.484 ± 0.012)MAX.11.00(0.433)MAX.(0.158)4.00MAX.1.78 ± 0.15(0.070 ± 0.006)1.00 ± 0.152.540.75 ± 0.25(0.039 ± 0.006)(0.100)(0.030 ± 0.010)0.254+ 0.076- 0.0051BSC(0.010+ 0.003)- 0.002)DIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).7° NOM.Solder Reflow Temperature Profile (HCPL-06XX andGull Wing Surface Mount Option 300 Parts)
260240220∆T = 145°C, 1°C/SEC200∆T = 115°C, 0.3°C/SECC°180 – E160RU140TA120RE100PM80ET60∆T = 100°C, 1.5°C/SEC402000123456789101112TIME – MINUTESNote: Use of nonchlorine activated fluxes is highly recommended.
1-151
元器件交易网www.cecb2b.com
Regulatory Information
The 6N137, HCPL-26XX/06XX/46XX, and HCNW137/26XX havebeen approved by the followingorganizations:
UL
Recognized under UL 1577,Component RecognitionProgram, File E55361.
CSA
Approved under CSA ComponentAcceptance Notice #5, File CA88324.
VDE
Approved according to VDE
0884/06.92. (HCPL-2611 Option060 and HCNW137/26X1 only)
BSI
Certification according toBS415:1994
(BS EN60065:1994),BS7002:1992
(BS EN60950:1992) andEN41003:1993 for Class IIapplications. (HCNW137/26X1only)
Insulation and Safety Related Specifications
Parameter SymbolMinimum ExternalL(101)Air Gap (ExternalClearance)
Minimum ExternalL(102)Tracking (ExternalCreepage)
Minimum InternalPlastic Gap
(Internal Clearance)
8-pin DIP (300 Mil)Value7.1
SO-8Value4.9
Widebody(400 Mil)ValueUnits9.6mm
Conditions
Measured from input terminalsto output terminals, shortestdistance through air.
Measured from input terminalsto output terminals, shortestdistance path along body.Through insulation distance,conductor to conductor, usuallythe direct distance between thephotoemitter and photodetectorinside the optocoupler cavity.Measured from input terminalsto output terminals, alonginternal cavity.
DIN IEC 112/VDE 0303 Part 1
7.44.810.0mm
0.080.081.0mm
Minimum InternalTracking (InternalCreepage)
Tracking Resistance(ComparativeTracking Index)Isolation Group
NANA4.0mm
CTI200200200Volts
IIIaIIIaIIIa
Material Group
(DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
1-152
元器件交易网www.cecb2b.com
VDE 0884 Insulation Related Characteristics(HCPL-2611 Option 060 Only)
DescriptionInstallation classification per DIN VDE 0110/1.89, Table 1for rated mains voltage ≤300 V rmsfor rated mains voltage ≤450 V rmsClimatic ClassificationPollution Degree (DIN VDE 0110/1.89)Maximum Working Insulation VoltageInput to Output Test Voltage, Method b*VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,Partial Discharge < 5 pCInput to Output Test Voltage, Method a*VIORM x 1.5 = VPR, Type and sample test,tm = 60 sec, Partial Discharge < 5 pCHighest Allowable Overvoltage*(Transient Overvoltage, tini = 10 sec)Safety Limiting Values(Maximum values allowed in the event of a failure,also see Figure 16, Thermal Derating curve.)Case TemperatureInput CurrentOutput PowerInsulation Resistance at TS, VIO = 500 VSymbolCharacteristicI-IVI-III55/85/2126301181UnitsVIORMVPRVPRVIOTMV peakV peakV peakV peak9456000IS,INPUTPS,OUTPUTRSTS175230600≥109°CmAmWΩ*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for adetailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits inapplication.
VDE 0884 Insulation Related Characteristics (HCNW137/2601/2611 Only)
DescriptionInstallation classification per DIN VDE 0110/1.89, Table 1for rated mains voltage ≤600 V rmsfor rated mains voltage ≤1000 V rmsClimatic Classification (DIN IEC 68 part 1)Pollution Degree (DIN VDE 0110/1.89)Maximum Working Insulation VoltageInput to Output Test Voltage, Method b*VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,Partial Discharge < 5 pCInput to Output Test Voltage, Method a*VIORM x 1.5 = VPR, Type and sample test,tm = 60 sec, Partial Discharge < 5 pCHighest Allowable Overvoltage*(Transient Overvoltage, tini = 10 sec)Safety Limiting Values(Maximum values allowed in the event of a failure,also see Figure 16, Thermal Derating curve.)Case TemperatureInput CurrentOutput PowerInsulation Resistance at TS, VIO = 500 VSymbolCharacteristicI-IVI-III55/100/21214142651UnitsVIORMVPRVPRVIOTMV peakV peakV peakV peak21218000IS,INPUTPS,OUTPUTRSTS150400700≥109°CmAmWΩ*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for adetailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits inapplication.
1-153
元器件交易网www.cecb2b.com
Absolute Maximum Ratings* (No Derating Required up to 85°C)
ParameterStorage TemperatureOperating Temperature†Average Forward Input CurrentSymbolTSTAIFPackage**Min.-55-40Max.1258520Units°C°CmANoteReverse Input VoltageInput Power DissipationSupply Voltage(1 Minute Maximum)Enable Input Voltage (Not toExceed VCC by more than500 mV)Enable Input CurrentOutput Collector CurrentOutput Collector Voltage(Selection for Higher OutputVoltages up to 20 V is Available.)Output Collector PowerDissipationVRPIVCCVESingle 8-Pin DIPSingle SO-8WidebodyDual 8-Pin DIPDual SO-88-Pin DIP, SO-8WidebodyWidebody21553407VCC + 0.5VmWVV1, 31Single 8-Pin DIPSingle SO-8WidebodyIEIOVO5507mAmAV11POLead Solder Temperature(Through Hole Parts Only)TLSSingle 8-Pin DIPSingle SO-8WidebodyDual 8-Pin DIPDual SO-88-Pin DIPWidebody85mW60260°C for 10 sec., 1.6 mm below seating plane260°C for 10 sec.,up to seating planeSee Package OutlineDrawings section1, 4Solder Reflow TemperatureProfile (Surface Mount Parts Only)SO-8 andOption 300*JEDEC Registered Data (for 6N137 only).
**Ratings apply to all devices except otherwise noted in the Package column.†0°C to 70°C on JEDEC Registration.
Recommended Operating Conditions
Parameter
Input Current, Low LevelInput Current, High Level[1]Power Supply Voltage
Low Level Enable Voltage†High Level Enable Voltage†Operating TemperatureFan Out (at RL = 1 kΩ)[1]Output Pull-up Resistor
SymbolIFL*IFH**VCCVELVEHTANRL
Min.054.502.0-40330
Max.250155.50.8VCC8554 k
UnitsµAmAVVV°CTTL Loads
Ω
*The off condition can also be guaranteed by ensuring that VFL ≤0.8 volts.
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permitat least a 20% LED degradation guardband.†For single channel products only.
1-154
元器件交易网www.cecb2b.com
Electrical Specifications
Over recommended temperature (TA = -40°C to +85°C) unless otherwise specified. All Typicals at VCC = 5 V,TA = 25°C. All enable test conditions apply to single channel products only. See note 5.
ParameterHigh Level OutputCurrentInput ThresholdCurrentLow Level OutputVoltageHigh Level SupplyCurrentSym.IOH*ITHPackageAllSingle ChannelWidebodyDual Channel8-Pin DIPSO-8WidebodySingle ChannelDual ChannelLow Level SupplyCurrentICCLSingle ChannelDual ChannelHigh Level EnableCurrentLow Level EnableCurrentHigh Level EnableVoltageLow Level EnableVoltageInput ForwardVoltageIEHIEL*VEHVELVF8-Pin DIPSO-8Widebody8-Pin DIPSO-8Widebody8-Pin DIPSO-8Widebody8-Pin DIPSO-8Widebody1.41.31.251.253-1.6-1.96070pFf = 1 MHz, VF = 0 V1mV/°C1.51.642.00.81.75*1.801.852.05Single ChannelMin.Typ.5.52.02.50.350.47.06.5109.08.513-0.7-0.910.0*1513.0*21-1.6-1.6mAmAVVVTA = 25°CTA = 25°CVIR = 10 µAIR = 100 µA, TA = 25°C IF = 10 mAMax.1005.0UnitsµAmATest ConditionsVCC = 5.5 V, VE = 2.0 V,VO = 5.5 V, IF = 250 µAVCC = 5.5 V, VE = 2.0 V,VO = 0.6 V,IOL (Sinking) = 13 mAVCC = 5.5 V, VE = 2.0 V,IF = 5 mA,IOL (Sinking) = 13 mAVE = 0.5 VVCC = 5.5 VIF = 0 mAVE = VCCBothChannelsVE = 0.5 VVCC = 5.5 VIF = 10 mAVE = VCCBothChannelsVCC = 5.5 V, VE = 2.0 VVCC = 5.5 V, VE = 0.5 VFig.12, 3 Note1, 6,1919VOL*0.6V2, 3,4, 51, 19ICCHmA7mA8919IF = 10 mA6, 71Input ReverseBreakdownVoltageInput DiodeTemperatureCoefficientInput CapacitanceBVR*1∆VF/∆TACIN71*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to +70°C. HP specifies -40°C to +85°C.
1-155
元器件交易网www.cecb2b.com
Switching Specifications (AC)
Over Recommended Temperature (TA = -40°C to +85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.All Typicals at TA = 25°C, VCC = 5 V.
ParameterPropagation DelayTime to HighOutput LevelPropagation DelayTime to LowOutput LevelPulse WidthDistortionPropagation DelaySkewOutput RiseTime (10-90%)Output FallTime (90-10%)Propagation DelayTime of Enablefrom VEH to VELPropagation DelayTime of Enablefrom VEL to VEHSym.tPLHPackage**Min.Typ.2048Max.75*10075*1003540402410Single Channel30nsnsnsnsRL = 350 Ω,CL = 15 pF,VEL = 0 V, VEH = 3 V121213,14UnitsTest ConditionsFig. NotensTA = 25°CRL = 350 Ω8, 9,1, 10,19CL = 15 pF10nsTA = 25°C1, 11,198, 9,13, 1910,1112, 13,191, 191, 1914tPHL2550|tPHL - tPLH|8-Pin DIPSO-8Widebody3.5nstPSKtrtftELHtEHLSingle Channel20ns15*JEDEC registered data for the 6N137.
**Ratings apply to all devices except otherwise noted in the Package column.
ParameterLogic HighCommonModeTransientImmunityLogic LowCommonModeTransientImmunitySym.Device|CMH|6N137HCPL-2630HCPL-0600/0630HCNW137HCPL-2601/2631HCPL-0601/0631HCNW2601HCPL-2611/4661HCPL-0611/0661HCNW2611|CML|6N137HCPL-2630HCPL-0600/0630HCNW137HCPL-2601/2631HCPL-0601/0631HCNW2601HCPL-2611/4661HCPL-0611/0661HCNW2611Min.Typ.Units10,000V/µs Test Conditions|VCM| = 10 VVCC = 5 V, IF = 0 mA,VO(MIN) = 2 V,RL = 350 Ω, TA = 25°C|VCM| = 50 V|VCM| = 1 kVFig.15Note1, 16,18, 195,00010,00010,00015,00010,000V/µs|VCM| = 10 VVCC = 5 V, IF = 7.5 mA,VO(MAX) = 0.8 V,RL = 350 Ω, TA = 25°C151, 17,18, 195,00010,000|VCM| = 50 V|VCM| = 1 kV10,00015,0001-156
元器件交易网www.cecb2b.com
Package Characteristics
All Typicals at TA = 25°C.
ParameterInput-OutputInsulationInput-OutputMomentary With-stand Voltage**Input-OutputResistanceInput-OutputCapacitanceInput-InputInsulationLeakage CurrentResistance(Input-Input)Capacitance(Input-Input)Sym.II-O*VISOPackageSingle 8-Pin DIPSingle SO-88-Pin DIP, SO-8WidebodyOPT 020†8-Pin DIP, SO-8Widebody8-Pin DIP, SO-8WidebodyDual Channel25005000500010121011CI-OII-I0.60.50.005pF0.6µARH ≤ 45%, t = 5 s,VI-I = 500 V10121013Min.Typ.Max.1UnitsµAV rms Test Conditions45% RH, t = 5 s,VI-O = 3 kV dc, TA = 25°CRH ≤ 50%, t = 1 min,TA = 25°CVI-O = 500 V dcTA = 25°CTA = 100°Cf = 1 MHz, TA = 25°CFig.Note20, 2120, 2120, 221, 20,231, 20,2324RI-OΩRI-ICI-IDual ChannelDual 8-Pin DIPDual SO-810110.030.25ΩpFf = 1 MHz2424*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to 70°C. HP specifies -40°C to 85°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-outputcontinuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”†For 6N137, HCPL-2601/2611/2630/2631/4661 only.
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current doesnot exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current doesnot exceed 15 mA.
4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated inFigure 17. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The JEDEC registration for the 6N137 specifies a maximum IOH of 250 µA. HP guarantees a maximum IOH of 100 µA.7. The JEDEC registration for the 6N137 specifies a maximum ICCH of 15 mA. HP guarantees a maximum ICCH of 10 mA.8. The JEDEC registration for the 6N137 specifies a maximum ICCL of 18 mA. HP guarantees a maximum ICCL of 13 mA.9. The JEDEC registration for the 6N137 specifies a maximum IEL of –2.0 mA. HP guarantees a maximum IEL of -1.6 mA.
10. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
11. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
12. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified
test conditions.
13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.14. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V
point on the rising edge of the output pulse.
15. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point
on the falling edge of the output pulse.
16. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state
(i.e., VO > 2.0 V).
17. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., VO < 0.8 V).
18. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM(p-p).
1-157
元器件交易网www.cecb2b.com
19. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in
improved CMR performance. For single channel products only.
20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 Vrms for one second
(leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge(Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.
22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for one second
(leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge(Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.
23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products
only.
24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
IOH – HIGH LEVEL OUTPUT CURRENT – µA156VO – OUTPUT VOLTAGE – VVCC = 5.5 VVO = 5.5 VVE = 2.0 V*IF = 250 µA8-PIN DIP, SO-8VCC = 5 VTA = 25 °C6VO – OUTPUT VOLTAGE – VWIDEBODYVCC = 5 VTA = 25 °C545410* FOR SINGLE CHANNEL PRODUCTS ONLYRL = 350 Ω3RL = 1 KΩ2RL = 4 KΩ10RL = 350 Ω3RL = 1 KΩ2RL = 4 KΩ1050-60-40-2002040608010001234560123456TA – TEMPERATURE – °CIF – FORWARD INPUT CURRENT – mA IF – FORWARD INPUT CURRENT – mA Figure 1. Typical High Level OutputCurrent vs. Temperature.
Figure 2. Typical Output Voltage vs. Forward Input Current.
ITH – INPUT THRESHOLD CURRENT – mA654ITH – INPUT THRESHOLD CURRENT – mA8-PIN DIP, SO-8VCC = 5.0 VVO = 0.6 V654321WIDEBODYVCC = 5.0 VVO = 0.6 VRL = 350 KΩ3210-60-40-20RL = 1 KΩRL = 1 KΩRL = 350 Ω RL = 4 KΩ020406080100RL = 4 KΩ0204060801000-60-40-20TA – TEMPERATURE – °CTA – TEMPERATURE – °CFigure 3. Typical Input Threshold Current vs. Temperature.
1-158
元器件交易网www.cecb2b.com
0.80.70.60.50.40.30.20.1IOL – LOW LEVEL OUTPUT CURRENT – mAVOL – LOW LEVEL OUTPUT VOLTAGE – VVOL – LOW LEVEL OUTPUT VOLTAGE – V8-PIN DIP, SO-8VCC = 5.5 VVE = 2.0 V*IF = 5.0 mA* FOR SINGLE CHANNEL PRODUCTS ONLY0.80.70.60.50.40.30.20.10-60-40-20WIDEBODYVCC = 5.5 VVE = 2.0 VIF = 5.0 mAIO = 16 mAIO = 12.8 mA70
VCC = 5.0 VVE = 2.0 V*VOL = 0.6 V* FOR SINGLE CHANNEL PRODUCTS ONLYIF = 10-15 mA60
IO = 16 mAIO = 12.8 mA50
IO = 9.6 mAIO = 6.4 mAIO = 9.6 mAIO = 6.4 mA40
IF = 5.0 mA0-60-40-2002040608010002040608010020
-60-40-20020406080100TA – TEMPERATURE – °CTA – TEMPERATURE – °CTA – TEMPERATURE – °C
Figure 4. Typical Low Level Output Voltage vs. Temperature.
Figure 5. Typical Low Level OutputCurrent vs. Temperature.
1000IF – FORWARD CURRENT – mA8-PIN DIP, SO-8IF – FORWARD CURRENT – mA110100101.00.10.01WIDEBODYTA = 25 °CIF+VF–TA = 25 °C100101.00.10.01IF+VF–0.0011.11.21.31.41.51.60.0011.21.31.41.51.61.7VF – FORWARD VOLTAGE – VVF – FORWARD VOLTAGE – VFigure 6. Typical Input Diode Forward Characteristic.
dVF/dT – FORWARD VOLTAGE TEMPERATURE COEFFICIENT – mV/°C-2.2-2.0-1.8-1.6-1.4-1.20.1dVF/dT – FORWARD VOLTAGE TEMPERATURE COEFFICIENT – mV/°C-2.48-PIN DIP, SO-8-2.3WIDEBODY-2.2-2.1-2.0-1.9-1.80.1110100110100IF – PULSE INPUT CURRENT – mAIF – PULSE INPUT CURRENT – mAFigure 7. Typical Temperature Coefficient of Forward Voltage vs. Input Current.
1-159
元器件交易网www.cecb2b.com
SINGLE CHANNELPULSE GEN.Z = 50 ΩO t = t = 5 nsrfIF12INPUTMONITORINGNODERM34VCC876PULSE GEN.Z = 50 ΩO t = t = 5 nsrf+5 VIF1DUAL CHANNELVCC8+5 V0.1µFBYPASSRLINPUTMONITORINGNODERL23RM4GND570.1µFBYPASSCL*OUTPUT V OMONITORING NODE*CLGND5OUTPUT V OMONITORING NODE6*CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE.INPUTIFtPHLOUTPUTVOtPLHI = 7.50 mA FI = 3.75 mAF1.5 VFigure 8. Test Circuit for tPHL and tPLH.
100tP – PROPAGATION DELAY – nstP – PROPAGATION DELAY – nsVCC = 5.0 VIF = 7.5 mAtPLH , RL = 4 KΩ10590VCC = 5.0 VTA = 25°CtPLH , RL = 4 KΩ80tPHL , RL = 350 Ω1 KΩ604 KΩ40207560tPLH , RL = 350 Ω tPLH , RL = 1 KΩtPHL , RL = 350 Ω1 KΩ4 KΩ579111315IF – PULSE INPUT CURRENT – mAtPLH , RL = 1 KΩtPLH , RL = 350 Ω 45300-60-40-20020406080100TA – TEMPERATURE – °CFigure 9. Typical Propagation Delayvs. Temperature.Figure 10. Typical Propagation Delayvs. Pulse Input Current.
PWD – PULSE WIDTH DISTORTION – ns4030VCC = 5.0 VIF = 7.5 mA20RL = 350 Ω tr, tf – RISE, FALL TIME – nsRL = 4 kΩVCC = 5.0 VIF = 7.5 mAtRISEtFALL30029060RL = 4 kΩ10RL = 1 kΩ40200-60-40-20RL = 350 ΩRL = 350 Ω, 1 kΩ, 4 kΩ0204060801000RL = 1 kΩ-10-60-40-20020406080100TA – TEMPERATURE – °CTA – TEMPERATURE – °CFigure 11. Typical Pulse WidthDistortion vs. Temperature.Figure 12. Typical Rise and Fall Timevs. Temperature.
1-160
元器件交易网www.cecb2b.com
PULSE GEN.Z = 50 ΩO t = t = 5 nsfrINPUT VEMONITORING NODE+5 V1VCC870.1 µFBYPASSRLOUTPUT V OMONITORING NODE3.0 VINPUTVEtEHLOUTPUTVOtELH1.5 V7.5 mAIF236*CL51.5 V4GND*C IS APPROXIMATELY 15 pF WHICH INCLUDES L PROBE AND STRAY WIRING CAPACITANCE.Figure 13. Test Circuit for tEHL andtELH.
tE – ENABLE PROPAGATION DELAY – ns120VCC = 5.0 VVEH = 3.0 VVEL = 0 VI90F = 7.5 mAtELH, RL = 4 kΩ60tELH, RL = 1 kΩ30tELH, RL = 350 ΩtEHL, RL = 350 Ω, 1 kΩ, 4 kΩ0-60-40-20020406080100TA – TEMPERATURE – °CFigure 14. Typical Enable PropagationDelay vs. Temperature.
IFSINGLE CHANNELIFBAVFF234GNDVCM+–PULSEGENERATORZ = 50 ΩO7651VCC80.1 µFBYPASSRLOUTPUT V OMONITORING NODE+5 VBA12VFF34DUAL CHANNELVCC8RL76GNDVCM+–PULSEGENERATORZ = 50 ΩO50.1 µFBYPASS+5 VOUTPUT V OMONITORING NODEVCMVOV (PEAK)CM0 V5 VSWITCH AT A: I = 0 mAFV (MIN.)OSWITCH AT B: I = 7.5 mAFV (MAX.)O0.5 VCMLCMHVOFigure 15. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
1-161
元器件交易网www.cecb2b.com
OUTPUT POWER – PS, INPUT CURRENT – ISOUTPUT POWER – PS, INPUT CURRENT – IS8007006005004003002001000025HCPL-2611 OPTION 060PS (mW)IS (mA)HCNWXXXXPS (mW)80070060050040030020010000255075100125150175IS (mA)5075100125150175200TS – CASE TEMPERATURE – °CTS – CASE TEMPERATURE – °CFigure 16. Thermal Derating Curve, Dependence of Safety Limiting Value withCase Temperature per VDE 0884.
GND BUS (BACK)VCC BUS (FRONT)NCENABLE0.1µFNCOUTPUT10 mm MAX.(SEE NOTE 5)SINGLE CHANNELDEVICE ILLUSTRATED.Figure 17. Recommended Printed Circuit Board Layout.
1-162
元器件交易网www.cecb2b.com
SINGLE CHANNEL DEVICEVCC15 V85 VVCC2470 Ω390 ΩIF2+6D1*VF0.1 µFBYPASSGND 1–35SHIELDVGND 2E172*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.DUAL CHANNEL DEVICECHANNEL 1 SHOWNVCC15 V85 VVCC2
470 Ω390 ΩIF1+7D1*VF0.1 µFBYPASSGND 1–25SHIELDGND 212Figure 18. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.
1-163
元器件交易网www.cecb2b.com
Propagation Delay, Pulse-Width Distortion andPropagation Delay Skew
Propagation delay is a figure ofmerit which describes how
quickly a logic signal propagatesthrough a system. The propaga-tion delay from low to high (tPLH)is the amount of time required foran input signal to propagate tothe output, causing the output tochange from low to high.
Similarly, the propagation delayfrom high to low (tPHL) is theamount of time required for theinput signal to propagate to theoutput causing the output tochange from high to low (seeFigure8).
Pulse-width distortion (PWD)
results when tPLH and tPHL differ invalue. PWD is defined as thedifference between tPLH and tPHLand often determines the
maximum data rate capability of atransmission system. PWD can beexpressed in percent by dividingthe PWD (in ns) by the minimumpulse width (in ns) being
transmitted. Typically, PWD onthe order of 20-30% of the
minimum pulse width is tolerable;the exact figure depends on theparticular application (RS232,RS422, T-l, etc.).
Propagation delay skew, tPSK, isan important parameter to
consider in parallel data applica-
1-164
tions where synchronization ofsignals on parallel data lines is aconcern. If the parallel data isbeing sent through a group ofoptocouplers, differences in
propagation delays will cause thedata to arrive at the outputs of theoptocouplers at different times. Ifthis difference in propagationdelays is large enough, it willdetermine the maximum rate atwhich parallel data can be sentthrough the optocouplers.Propagation delay skew is definedas the difference between theminimum and maximum
propagation delays, either tPLH ortPHL, for any given group of
optocouplers which are operatingunder the same conditions (i.e.,the same drive current, supplyvoltage, output load, andoperating temperature). Asillustrated in Figure 19, if theinputs of a group of optocouplersare switched either ON or OFF atthe same time, tPSK is the
difference between the shortestpropagation delay, either tPLH ortPHL, and the longest propagationdelay, either tPLH or tPHL.
As mentioned earlier, tPSK candetermine the maximum paralleldata transmission rate. Figure 20is the timing diagram of a typicalparallel data application with boththe clock and the data lines beingsent through optocouplers. Thefigure shows data and clock
signals at the inputs and outputsof the optocouplers. To obtain themaximum data transmission rate,both edges of the clock signal arebeing used to clock the data; ifonly one edge were used, theclock signal would need to betwice as fast.
Propagation delay skew repre-sents the uncertainty of where anedge might be after being sentthrough an optocoupler. Figure20 shows that there will be
uncertainty in both the data andthe clock lines. It is importantthat these two areas of uncertaintynot overlap, otherwise the clocksignal might arrive before all ofthe data outputs have settled, orsome of the data outputs maystart to change before the clocksignal has arrived. From theseconsiderations, the absolute
minimum pulse width that can besent through optocouplers in aparallel application is twice tPSK. Acautious design should use aslightly longer pulse width toensure that any additionaluncertainty in the rest of the
circuit does not cause a problem.The tPSK specified optocouplersoffer the advantages of
guaranteed specifications forpropagation delays, pulsewidthdistortion and propagation delayskew over the recommendedtemperature, input current, andpower supply ranges.
元器件交易网www.cecb2b.com
IF50%VO1.5 VIF50%VO1.5 VtPSKFigure 19. Illustration of PropagationDelay Skew - tPSK.DATAINPUTSCLOCKDATAOUTPUTStPSKCLOCKtPSKFigure 20. Parallel Data TransmissionExample.
1-165
因篇幅问题不能全部显示，请点此查看更多更全内容