Logic simulation

专利名称：Logic simulation

发明人：Kimio Ooe,Nobutaka Amano,Takashige

Kubo,Kaoru Moriwaki

申请号：US07/042233申请日：19870424公开号：US04891773A公开日：19900102

摘要：In a logic simulation method for performing logic simulation of a logic circuitincluding a circuit with unknown internal logic, the circuit itself with the unknown internallogic is used. The internal status of the circuit is set at an objective status using theinterrupt operation afforded by the circuit and thereafter, input signal value is applied tothe circuit to obtain a resultant output. For other logic circuits without unknown internallogic, software logic simulation is performed. During such software logic simulation, theactual circuit with unknown internal logic is called.

申请人：HITACHI, LTD.,HITACHI MICROCOMPUTER ENGINEERING LTD.

代理机构：Antonelli, Terry & Wands

更多信息请下载全文后查看