24LC16-IIC

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24LC16B16K 2.5V I2C™ Serial EEPROM

FEATURES

•Single supply with operation down to 2.5V•Low power CMOS technology-1 mA active current typical

-10 µA standby current typical at 5.5V-5 µA standby current typical at 3.0V

•Organized as 8 blocks of 256 bytes (8 x 256 x 8)•2-wire serial interface bus, I2C™ compatible•Schmitt trigger inputs for noise suppression

•Output slope control to eliminate ground bounce•100 kHz (2.5V) and 400 kHz (5V) compatibility•Self-timed write cycle (including auto-erase)•Page-write buffer for up to 16 bytes

•2 ms typical write cycle time for page-write•Hardware write protect for entire memory•Can be operated as a serial ROM•Factory programming (QTP) available•ESD protection > 4,000V

•10,000,000 erase/write cycles guaranteed•Data retention > 200 years

•8-pin DIP, 8-lead or 14-lead SOIC packages•Available for extended temperature ranges-Commercial (C):0°Cto+70°C-Industrial (I): -40°Cto+85°C

PACKAGE TYPESPDIPA0A1A2VSS124LC16B2348765VCCWPSCLSDASOICA0A1A2VSS14-lead SOICNCA0A1NCA2VSSNC123424LC16B8765VCCWPSCLSDA1234567141312111098NCVCCWPNCSCLSDANC24LC16BDESCRIPTION

The Microchip Technology Inc. 24LC16B is a 16K bit

Electrically Erasable PROM. The device is organizedas eight blocks of 256 x 8 bit memory with a 2-wireserial interface. Low voltage design permits operationdown to 2.5 volts with standby and active currents ofonly 5 µA and 1 mA respectively. The 24LC16B alsohas a page-write capability for up to 16 bytes of data.The 24LC16B is available in the standard 8-pin DIP andboth 8-lead and 14-lead surface mount SOIC pack-ages.

BLOCK DIAGRAMWPHV GENERATORI/OCONTROLLOGICMEMORYCONTROLLOGICXDECEEPROM ARRAYPAGE LATCHESSDASCLYDECVCCVSSSENSE AMPR/W CONTROLI2C is a trademark of Philips Corporation.

ThisdocumentwascreatedwithFrameMaker404

24LC16B

1.0

1.1

ELECTRICAL CHARACTERISTICS

Maximum Ratings*TABLE 1-1:

NameVSSSDASCLWPVCCA0, A1, A2

PIN FUNCTION TABLE

Function

Ground

Serial Address/Data I/OSerial Clock

Write Protect Input

+2.5V to 5.5V Power SupplyNo Internal Connection

VCC...................................................................................7.0VAll inputs and outputs w.r.t. VSS...............-0.3V to VCC +1.0VStorage temperature.....................................-65˚C to +150˚CAmbient temp. with power applied................-65˚C to +125˚CSoldering temperature of leads (10 seconds).............+300˚CESD protection on all pins..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or anyother conditions above those indicated in the operational listingsof this speciﬁcation is not implied. Exposure to maximum ratingconditions for extended periods may affect device reliability.

TABLE 1-2:DC CHARACTERISTICS

Vcc = +2.5V to +5.5V

Commercial (C): Tamb = 0˚C to +70˚CIndustrial (I): Tamb = -40˚C to +85˚C

Parameter

SymbolVIH

VILVHYSVOLILIILOCIN, COUTICC writeICC readICCS

Min.7 VCC—.05 VCC—-10-10—————

Max—.3 VCC—.401010103130100

UnitsVVVVµAµApFmAmAµAµA

Conditions

WP, SCL and SDA pins:

High level input voltageLow level input voltage

Hysteresis of Schmitt trigger inputs

Low level output voltageInput leakage currentOutput leakage currentPin capacitance(all inputs/outputs)Operating currentStandby current

Note:

(Note)

IOL = 3.0 mA, VCC = 2.5VVIN = .1V to VCCVOUT = .1V to VCCVCC = 5.0V (Note)

Tamb = 25˚C, FCLK = 1MHzVCC = 5.5V, SCL = 400 kHzVCC = 3.0V, SDA = SCL = VCCVCC = 5.5V, SDA = SCL = VCC

This parameter is periodically sampled and not 100% tested.

24LC16B

TABLE 1-3:AC CHARACTERISTICS

STANDARD MODEMin

Max100——1000300—————3500—

—40004700——4000470002504000—4700

Vcc = 4.5V - 5.5VFAST MODEMin—6001300——6006000100600—1300

Max400——300300—————900—

kHznsnsnsnsnsnsnsnsnsnsns

Parameter

Clock frequencyClock high timeClock low time

SDA and SCL rise timeSDA and SCL fall timeSTART condition hold time

SymbolFCLKTHIGHTLOWTRTFTHD:STA

UnitsRemarks

START condition setup timeTSU:STAData input hold timeData input setup time

STOP condition setup timeOutput valid from clockBus free time

THD:DATTSU:DATTSU:STOTAATBUF

(Note 1)(Note 1)

After this period the ﬁrst clock pulse is generatedOnly relevant for repeated START condition

Output fall time from VIH min to VIL max

Input ﬁlter spike suppres-sion (SDA and SCL pins)Write cycle timeEndurance

TOFTSPTWR—

———10M

2505010—

20 +0.1 CB——10M

2505010—

nsns

(Note 2)

Time the bus must be free before a new transmission can start

(Note 1), CB ≤ 100 pF(Note 3)

msByte or Page mode

cycles25°C, Vcc = 5.0V, Block

Mode (Note 4)

Note1:Not 100% tested. CB = total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.3:The combined TSP and VHYS speciﬁcations are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a TI speciﬁcation for standard operation.

4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

24LC16B

2.0

FUNCTIONAL DESCRIPTION

3.4

Data Valid (D)The 24LC16B supports a Bi-directional 2-wire bus anddata transmission protocol. A device that sends dataonto the bus is deﬁned as transmitter, and a devicereceiving data as receiver. The bus has to be controlledby a master device which generates the serial clock(SCL), controls the bus access, and generates theSTART and STOP conditions, while the 24LC16Bworks as slave. Both, master and slave can operate astransmitter or receiver but the master device deter-mines which mode is activated.

The state of the data line represents valid data when,after a START condition, the data line is stable for theduration of the HIGH period of the clock signal.The data on the line must be changed during the LOWperiod of the clock signal. There is one clock pulse perbit of data.

Each data transfer is initiated with a START conditionand terminated with a STOP condition. The number ofthe data bytes transferred between the START andSTOP conditions is determined by the master deviceand is theoretically unlimited, although only the last six-teen will be stored when doing a write operation. Whenan overwrite does occur it will replace data in a ﬁrst inﬁrst out fashion.

3.0BUS CHARACTERISTICS

The following bus protocol has been deﬁned:•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.Accordingly, the following bus conditions have beendeﬁned (Figure 3-1).

3.5AcknowledgeEach receiving device, when addressed, is obliged togenerate an acknowledge after the reception of eachbyte. The master device must generate an extra clockpulse which is associated with this acknowledge bit.Note:The 24LC16B does not generate anyacknowledge bits if an internal program-ming cycle is in progress.3.1Bus not Busy (A)Both data and clock lines remain HIGH.

3.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while theclock (SCL) is HIGH determines a START condition. Allcommands must be preceded by a START condition.

3.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while theclock (SCL) is HIGH determines a STOP condition. Alloperations must be ended with a STOP condition.

The device that acknowledges, has to pull down theSDA line during the acknowledge clock pulse in such away that the SDA line is stable LOW during the HIGHperiod of the acknowledge related clock pulse. Ofcourse, setup and hold times must be taken intoaccount. During reads, a master must signal an end ofdata to the slave by not generating an acknowledge biton the last byte that has been clocked out of the slave.In this case, the slave (24LC16B) will leave the data lineHIGH to enable the master to generate the STOP con-dition.

24LC16B

3.6

Device Addressing4.0

4.1

WRITE OPERATION

Byte WriteA control byte is the ﬁrst byte received following thestart condition from the master device. The control byteconsists of a four bit control code, for the 24LC16B thisis set as 1010 binary for read and write operations. Thenext three bits of the control byte are the block selectbits (B2, B1, B0). They are used by the master deviceto select which of the eight 256 word blocks of memoryare to be accessed. These bits are in effect the threemost signiﬁcant bits of the word address. It should benoted that the protocol limits the size of the memory toeight blocks of 256 words, therefore the protocol cansupport only one 24LC16B per system.

The last bit of the control byte deﬁnes the operation tobe performed. When set to one a read operation isselected, when set to zero a write operation is selected.Following the start condition, the 24LC16B monitors theSDA bus checking the device type identiﬁer beingtransmitted, upon a 1010 code the slave device outputsan acknowledge signal on the SDA line. Depending onthe state of the R/W bit, the 24LC16B will select a reador write operation. OperationReadWrite

Control Code10101010

Block SelectBlock AddressBlock Address

R/W10

Following the start condition from the master, thedevice code (4 bits), the block address (3 bits), and theR/W bit which is a logic low is placed onto the bus bythe master transmitter. This indicates to the addressedslave receiver that a byte with a word address will followafter it has generated an acknowledge bit during theninth clock cycle. Therefore the next byte transmitted bythe master is the word address and will be written intothe address pointer of the 24LC16B. After receivinganother acknowledge signal from the 24LC16B themaster device will transmit the data word to be writteninto the addressed memory location. The 24LC16Backnowledges again and the master generates a stopcondition. This initiates the internal write cycle, and dur-ing this time the 24LC16B will not generate acknowl-edge signals (Figure 4-1).

4.2Page Write FIGURE 3-2:

STARTCONTROL BYTE ALLOCATIONREAD/WRITESLAVE ADDRESSR/WAThe write control byte, word address and the ﬁrst databyte are transmitted to the 24LC16B in the same wayas in a byte write. But instead of generating a stop con-dition the master transmits up to 16 data bytes to the24LC16B which are temporarily stored in the on-chippage buffer and will be written into the memory after themaster has transmitted a stop condition. After thereceipt of each word, the four lower order addresspointer bits are internally incremented by one. Thehigher order seven bits of the word address remainsconstant. If the master should transmit more than 16words prior to generating the stop condition, theaddress counter will roll over and the previouslyreceived data will be overwritten. As with the byte writeoperation, once the stop condition is received an inter-nal write cycle will begin (Figure 4-2).

1010XXXX = Don’t careFIGURE 4-1:BUS ACTIVITYMASTERBYTE WRITESTARTCONTROLBYTEWORDADDRESSDATASTOPSDA LINESACKACKACKPBUS ACTIVITYFIGURE 4-2:BUS ACTIVITYMASTERPAGE WRITESTARTCONTROLBYTEWORDADDRESS (n)STOPDATA nDATA n + 1DATA n + 15SDA LINEBUS ACTIVITYSACKACKACKACKACKP© 1996 Microchip Technology Inc.DS20070G-page 5

24LC16B

5.0

ACKNOWLEDGE POLLING

7.0

READ OPERATION

Since the device will not acknowledge during a writecycle, this can be used to determine when the cycle iscomplete (this feature can be used to maximize busthroughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling canbe initiated immediately. This involves the master send-ing a start condition followed by the control byte for awrite command (R/W = 0). If the device is still busy withthe write cycle, then no ACK will be returned. If thecycle is complete, then the device will return the ACKand the master can then proceed with the next read orwrite command. See Figure 5-1 for ﬂow diagram.

Read operations are initiated in the same way as writeoperations with the exception that the R/W bit of theslave address is set to one. There are three basic typesof read operations: current address read, random read,and sequential read.

7.1Current Address ReadFIGURE 5-1:

ACKNOWLEDGE POLLING FLOWSendWrite CommandThe 24LC16B contains an address counter that main-tains the address of the last word accessed, internallyincremented by one. Therefore, if the previous access(either a read or write operation) was to address n, thenext current address read operation would access datafrom address n + 1. Upon receipt of the slave addresswith R/W bit set to one, the 24LC16B issues anacknowledge and transmits the eight bit data word. Themaster will not acknowledge the transfer but does gen-erate a stop condition and the 24LC16B discontinuestransmission (Figure 7-1).

7.2

Send StopCondition toInitiate Write CycleRandom ReadSend StartSend Control Bytewith R/W = 0Did DeviceAcknowledge(ACK = 0)?YESNextOperationRandom read operations allow the master to accessany memory location in a random manner. To performthis type of read operation, ﬁrst the word address mustbe set. This is done by sending the word address to the24LC16B as part of a write operation. After the wordaddress is sent, the master generates a start conditionfollowing the acknowledge. This terminates the writeoperation, but not before the internal address pointer isset. Then the master issues the control byte again butwith the R/W bit set to a one. The 24LC16B will thenissue an acknowledge and transmits the 8-bit dataword. The master will not acknowledge the transfer butdoes generate a stop condition and the 24LC16B dis-continues transmission (Figure 7-2).

NO7.3Sequential ReadSequential reads are initiated in the same way as a ran-dom read except that after the 24LC16B transmits theﬁrst data byte, the master issues an acknowledge asopposed to a stop condition in a random read. Thisdirects the 24LC16B to transmit the next sequentiallyaddressed 8-bit word (Figure 7-3).

To provide sequential reads the 24LC16B contains aninternal address pointer which is incremented by one atthe completion of each operation. This address pointerallows the entire memory contents to be serially readduring one operation.

6.0WRITE PROTECTION

The 24LC16B can be used as a serial ROM when theWP pin is connected to VCC. Programming will beinhibited and the entire memory will be write-protected.

7.4Noise ProtectionThe 24LC16B employs a VCC threshold detector circuitwhich disables the internal erase/write logic if the VCCis below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and ﬁltercircuits which suppress noise spikes to assure properdevice operation even on a noisy bus.

24LC16B

FIGURE 7-1:

CURRENT ADDRESS READ

BUS ACTIVITYMASTER

START

CONTROLBYTE

STOP

DATA n

SDA LINES

ACK

NO ACK

BUS ACTIVITY

FIGURE 7-2:RANDOM READSTARTSTARTSTOPBUS ACTIVITYMASTERCONTROLBYTEWORDADDRESS (n)CONTROLBYTEDATA (n)SDA LINESACKACKSACKNO ACKPBUS ACTIVITYFIGURE 7-3:BUS ACTIVITYMASTERSDA LINEBUS ACTIVITYSEQUENTIAL READCONTROLBYTEDATA nDATA n + 1DATA n + 2DATA n + XSTOPPACKACKACKACKNO ACK8.0

8.1

PIN DESCRIPTIONS

SDA Serial Address/Data Input/Output8.3WPThis pin must be connected to either VSS or VCC.If tied to Vss normal memory operation is enabled(read/write the entire memory 000-7FF).

If tied to VCC, WRITE operations are inhibited. Theentire memory will be write-protected. Read operationsare not affected.

This feature allows the user to use the 24LC16B as aserial ROM when WP is enabled (tied to VCC).

This is a Bi-directional pin used to transfer addressesand data into and data out of the device. It is an opendrain terminal, therefore the SDA bus requires a pullupresistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400kHz).

For normal data transfer SDA is allowed to change onlyduring SCL low. Changes during SCL high arereserved for indicating the START and STOP condi-tions.

8.4A0, A1, A28.2SCL Serial Clock These pins are not used by the 24LC16B. They maybe left ﬂoating or tied to either VSS or VCC.

This input is used to synchronize the data transfer fromand to the device.

24LC16B

NOTES:

24LC16B

NOTES:

24LC16B

NOTES:

24LC16B

24LC16B Product Identiﬁcation SystemTo order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listedsales ofﬁces. 24LC16B-/PPackage:P=Plastic DIP (300 mil Body), 8-leadSL=Plastic SOIC (150 mil Body), 14-leadSN=Plastic SOIC (150 mil Body), 8-leadBlank=0°C to +70°C I=-40°C to +85°C24LC16B24LC16BT16K I2C Serial EEPROM16K I2C Serial EEPROM (Tape and Reel)Temperature Range:Device:© 1996 Microchip Technology Inc.DS20070G-page 11

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9/3/96

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringementof patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo andname are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.DS20070G-page 12© 1996 Microchip Technology Inc.

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24LC16-IIC